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qemu-riscv (date)
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Last Modified: Mon Sep 30 2019 14:05:25 -0400
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September 30, 2019
Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
,
Alistair Francis
,
14:05
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Peter Maydell
,
07:42
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Peter Maydell
,
06:36
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Daniel P . Berrangé
,
05:26
September 27, 2019
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
17:54
Re: [Qemu-devel] [PATCH v3 33/50] target/riscv: fetch code with translator_ld
,
Alistair Francis
,
17:52
Re: [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
,
Alistair Francis
,
17:52
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Alistair Francis
,
17:34
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Richard Henderson
,
13:53
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Alistair Francis
,
13:28
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Richard Henderson
,
13:18
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Alistair Francis
,
13:08
Re: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
,
Richard W.M. Jones
,
09:50
Re: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
,
Richard W.M. Jones
,
09:50
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Mark Cave-Ayland
,
09:50
RE: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
,
Anup Patel
,
09:43
RE: [PATCH 0/2] RTC support for QEMU RISC-V virt machine
,
Anup Patel
,
08:54
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Philippe Mathieu-Daudé
,
05:10
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Gerd Hoffmann
,
04:56
Re: [PATCH v2 7/7] riscv/virt: Jump to pflash if specified
,
Bin Meng
,
03:57
Re: [PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device
,
Bin Meng
,
03:57
Re: [PATCH v2 5/7] riscv/virt: Manually define the machine
,
Bin Meng
,
03:57
Re: [PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
,
Bin Meng
,
03:57
Re: [PATCH v2 3/7] riscv/sifive_u: Manually define the machine
,
Bin Meng
,
03:57
Re: [PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region
,
Bin Meng
,
03:57
Re: [PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
,
Bin Meng
,
03:57
September 26, 2019
Re: [PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Bin Meng
,
23:08
[PATCH v1 1/1] target/riscv: Print CPU and privledge in disas
,
Alistair Francis
,
20:50
[PATCH v2 6/7] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
20:49
[PATCH v2 7/7] riscv/virt: Jump to pflash if specified
,
Alistair Francis
,
20:49
[PATCH v2 4/7] riscv/sifive_u: Add the start-in-flash property
,
Alistair Francis
,
20:49
[PATCH v2 5/7] riscv/virt: Manually define the machine
,
Alistair Francis
,
20:48
[PATCH v2 3/7] riscv/sifive_u: Manually define the machine
,
Alistair Francis
,
20:48
[PATCH v2 0/7] RISC-V: Add more machine memory
,
Alistair Francis
,
20:48
[PATCH v2 1/7] riscv/sifive_u: Add L2-LIM cache memory
,
Alistair Francis
,
20:48
[PATCH v2 2/7] riscv/sifive_u: Add QSPI memory region
,
Alistair Francis
,
20:48
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Alex Bennée
,
15:02
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Richard Henderson
,
13:12
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Christian Borntraeger
,
12:34
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Alistair Francis
,
12:17
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Alex Bennée
,
11:33
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Alex Bennée
,
11:28
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Alex Bennée
,
11:28
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Thomas Huth
,
10:26
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Daniel P . Berrangé
,
08:59
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Thomas Huth
,
03:56
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Peter Maydell
,
03:51
Re: [RFC PATCH] configure: deprecate 32 bit build hosts
,
Philippe Mathieu-Daudé
,
03:29
September 25, 2019
[PATCH V6] target/riscv: Ignore reserved bits in PTE for RV64
,
guoren
,
20:14
Re: [PATCH V5] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
19:46
[RFC PATCH] configure: deprecate 32 bit build hosts
,
Alex Bennée
,
19:31
Re: [PATCH V5] target/riscv: Ignore reserved bits in PTE for RV64
,
Alistair Francis
,
18:53
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Alistair Francis
,
18:52
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
12:16
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Jonathan Behrens
,
11:58
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
11:46
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Jonathan Behrens
,
11:20
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
08:29
[PATCH V5] target/riscv: Ignore reserved bits in PTE for RV64
,
guoren
,
08:05
Re: [PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64
,
Guo Ren
,
08:00
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Philippe Mathieu-Daudé
,
07:15
Re: [PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64
,
Bin Meng
,
05:58
[PATCH V4] target/riscv: Ignore reserved bits in PTE for RV64
,
guoren
,
05:21
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
05:11
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Markus Armbruster
,
05:01
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Bin Meng
,
01:35
Re: [PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
Alistair Francis
,
01:19
[PATCH V3] target/riscv: Bugfix reserved bits in PTE for RV64
,
guoren
,
00:48
RE: [PATCH v2 0/2] RTC support for QEMU RISC-V virt machine
,
Anup Patel
,
00:04
September 24, 2019
Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Alistair Francis
,
21:06
Re: [PATCH V2] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
21:03
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
21:00
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
20:59
Re: [PATCH V2] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
20:52
Re: [PATCH V2] target/riscv: Bugfix reserved bits in PTE for RV64
,
Alistair Francis
,
20:26
Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Alistair Francis
,
19:40
Re: [PATCH V2] target/riscv: Bugfix reserved bits in PTE for RV64
,
Alistair Francis
,
19:38
Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Palmer Dabbelt
,
16:04
Re: [Qemu-devel] [PATCH] atomic failures on qemu-system-riscv64
,
Alistair Francis
,
14:34
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Laszlo Ersek
,
14:06
Re: [RFC v2 0/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
12:10
Re: [RFC v2 0/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
11:50
Re: [RFC v2 0/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
11:46
Re: [RFC v2 0/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
11:44
Re: [RFC v2 0/9] error: auto propagated local_err
,
Eric Blake
,
11:30
Re: [RFC v2 0/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
10:12
Re: [PATCH v2 0/2] RTC support for QEMU RISC-V virt machine
,
Philippe Mathieu-Daudé
,
10:05
[PATCH v2 2/2] riscv: virt: Use Goldfish RTC device
,
Anup Patel
,
09:12
[PATCH v2 1/2] hw: timer: Add Goldfish RTC device
,
Anup Patel
,
09:12
[PATCH v2 0/2] RTC support for QEMU RISC-V virt machine
,
Anup Patel
,
09:12
Re: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
09:11
Re: [PATCH V2] target/riscv: Bugfix reserved bits in PTE for RV64
,
Guo Ren
,
09:11
[PATCH V2] target/riscv: Bugfix reserved bits in PTE for RV64
,
guoren
,
09:11
[PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
,
guoren
,
09:11
RE: [PATCH 1/2] hw: timer: Add Goldfish RTC device
,
Anup Patel
,
08:18
Re: [PATCH 1/2] hw: timer: Add Goldfish RTC device
,
Peter Maydell
,
07:31
RE: [PATCH 1/2] hw: timer: Add Goldfish RTC device
,
Anup Patel
,
07:17
Re: [RFC v2 6/9] scripts: add coccinelle script to use auto propagated errp
,
Vladimir Sementsov-Ogievskiy
,
06:36
Re: [PULL 11/48] riscv: Resolve full path of the given bios image
,
Peter Maydell
,
06:18
Re: [PATCH 1/2] hw: timer: Add Goldfish RTC device
,
Peter Maydell
,
05:51
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Philippe Mathieu-Daudé
,
05:32
[PATCH 2/2] riscv: virt: Use Goldfish RTC device
,
Anup Patel
,
04:43
[PATCH 1/2] hw: timer: Add Goldfish RTC device
,
Anup Patel
,
04:43
[PATCH 0/2] RTC support for QEMU RISC-V virt machine
,
Anup Patel
,
04:42
Re: [RFC v2 7/9] Use auto-propagated errp
,
Vladimir Sementsov-Ogievskiy
,
03:54
Re: [PATCH] target/riscv: Bugfix reserved bits in PTE for RV64
,
Alistair Francis
,
01:04
September 23, 2019
Re: [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property
,
Bin Meng
,
20:58
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Peter Maydell
,
18:22
Re: [RFC v2 6/9] scripts: add coccinelle script to use auto propagated errp
,
Eric Blake
,
17:31
Re: [RFC v2 7/9] Use auto-propagated errp
,
Eric Blake
,
16:31
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
16:09
Re: [RFC v2 6/9] scripts: add coccinelle script to use auto propagated errp
,
Eric Blake
,
16:06
Re: [RFC v2 1/9] error: auto propagated local_err
,
Eric Blake
,
15:59
Re: [RFC v2 0/9] error: auto propagated local_err
,
Eric Blake
,
15:48
Re: [RFC v2 5/9] net/net: fix local variable shadowing in net_client_init
,
Eric Blake
,
14:45
Re: [RFC v2 4/9] hw/core/loader-fit: fix freeing errp in fit_load_fdt
,
Eric Blake
,
14:42
Re: [RFC v2 2/9] qapi/error: add (Error **errp) cleaning APIs
,
Eric Blake
,
14:40
Re: [RFC v2 3/9] errp: rename errp to errp_in where it is IN-argument
,
Eric Blake
,
14:37
Re: [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook
,
Alistair Francis
,
13:53
Re: [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property
,
Alistair Francis
,
13:51
[RFC v2 0/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 4/9] hw/core/loader-fit: fix freeing errp in fit_load_fdt
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 7/9] Use auto-propagated errp
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 6/9] scripts: add coccinelle script to use auto propagated errp
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 2/9] qapi/error: add (Error **errp) cleaning APIs
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 8/9] fix-compilation: empty goto
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 3/9] errp: rename errp to errp_in where it is IN-argument
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 1/9] error: auto propagated local_err
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 9/9] fix-compilation: includes
,
Vladimir Sementsov-Ogievskiy
,
12:26
[RFC v2 5/9] net/net: fix local variable shadowing in net_client_init
,
Vladimir Sementsov-Ogievskiy
,
12:26
Re: [PATCH v1 6/6] riscv/virt: Jump to pflash if specified
,
Philippe Mathieu-Daudé
,
05:10
September 21, 2019
Re: [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property
,
Bin Meng
,
22:19
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Bin Meng
,
22:16
Re: [PATCH v2 1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes
,
Bin Meng
,
08:36
Re: [Qemu-devel] [PATCH v1 1/2] RISC-V: Handle bus errors in the page table walker
,
Philippe Mathieu-Daudé
,
05:09
Re: [Qemu-devel] [PATCH v1 2/2] RISC-V: Implement cpu_do_transaction_failed
,
Philippe Mathieu-Daudé
,
05:07
Re: [PATCH v2 2/2] riscv: sifive_u: Add ethernet0 to the aliases node
,
Philippe Mathieu-Daudé
,
04:52
Re: [PATCH v2 1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes
,
Philippe Mathieu-Daudé
,
04:51
[PATCH v2 1/2] riscv: hw: Drop "clock-frequency" property of cpu nodes
,
Bin Meng
,
01:42
[PATCH v2 2/2] riscv: sifive_u: Add ethernet0 to the aliases node
,
Bin Meng
,
01:42
September 20, 2019
Re: [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook
,
Palmer Dabbelt
,
18:48
Re: [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Palmer Dabbelt
,
18:40
Re: [PATCH v1 0/6] RISC-V: Add more machine memory
,
Palmer Dabbelt
,
18:40
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
18:17
Re: [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property
,
Alistair Francis
,
18:12
Re: [PATCH 2/2] riscv: sifive_u: Add ethernet0 to the aliases node
,
Alistair Francis
,
14:51
Re: [PATCH 1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes
,
Alistair Francis
,
14:51
Re: [PATCH] riscv: Skip checking CSR privilege level in debugger mode
,
Alistair Francis
,
14:47
[PATCH] riscv: Skip checking CSR privilege level in debugger mode
,
Bin Meng
,
10:47
Re: [PATCH v1 16/28] target/riscv: Add hypvervisor trap support
,
Palmer Dabbelt
,
10:01
[PATCH 1/2] riscv: sifive_u: Drop "clock-frequency" property of cpu nodes
,
Bin Meng
,
05:23
[PATCH 2/2] riscv: sifive_u: Add ethernet0 to the aliases node
,
Bin Meng
,
05:23
Re: [PATCH v1 1/6] riscv/sifive_u: Add L2-LIM cache memory
,
Bin Meng
,
01:15
Re: [PATCH v1 2/6] riscv/sifive_u: Add QSPI memory region
,
Bin Meng
,
01:15
Re: [PATCH v1 3/6] riscv/sifive_u: Manually define the machine
,
Bin Meng
,
01:15
Re: [PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property
,
Bin Meng
,
01:15
Re: [PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Bin Meng
,
01:15
Re: [PATCH v1 6/6] riscv/virt: Jump to pflash if specified
,
Bin Meng
,
01:15
September 19, 2019
[PATCH v1 5/6] riscv/virt: Add the PFlash CFI01 device
,
Alistair Francis
,
18:29
[PATCH v1 6/6] riscv/virt: Jump to pflash if specified
,
Alistair Francis
,
18:29
[PATCH v1 4/6] riscv/sifive_u: Add the start-in-flash property
,
Alistair Francis
,
18:29
[PATCH v1 3/6] riscv/sifive_u: Manually define the machine
,
Alistair Francis
,
18:29
[PATCH v1 2/6] riscv/sifive_u: Add QSPI memory region
,
Alistair Francis
,
18:29
[PATCH v1 0/6] RISC-V: Add more machine memory
,
Alistair Francis
,
18:29
[PATCH v1 1/6] riscv/sifive_u: Add L2-LIM cache memory
,
Alistair Francis
,
18:29
Re: [Qemu-devel] [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Jonathan Behrens
,
12:59
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Richard Henderson
,
10:50
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
,
Peter Maydell
,
08:27
September 18, 2019
Re: [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Alistair Francis
,
19:52
[Qemu-riscv] [PULL 10/48] riscv: Add a helper routine for finding firmware
,
Palmer Dabbelt
,
11:38
[Qemu-riscv] [PULL 48/48] gdbstub: riscv: fix the fflags registers
,
Palmer Dabbelt
,
11:29
[Qemu-riscv] [PULL 47/48] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
,
Palmer Dabbelt
,
11:29
[Qemu-riscv] [PULL 46/48] target/riscv: Fix mstatus dirty mask
,
Palmer Dabbelt
,
11:29
[Qemu-riscv] [PULL 44/48] riscv: sifive_u: Update model and compatible strings in device tree
,
Palmer Dabbelt
,
11:29
[Qemu-riscv] [PULL 42/48] riscv: sifive_u: Fix broken GEM support
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 45/48] target/riscv: Use both register name and ABI name
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate()
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 24/48] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 22/48] riscv: sifive_u: Remove the unnecessary include of prci header
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 21/48] riscv: roms: Remove executable attribute of opensbi images
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 20/48] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 19/48] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 18/48] riscv: hw: Change create_fdt() to return void
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 17/48] riscv: hw: Remove not needed PLIC properties in device tree
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 16/48] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 15/48] riscv: hw: Remove superfluous "linux, phandle" property
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 14/48] riscv: hw: Remove duplicated "hw/hw.h" inclusion
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 12/48] riscv: hmp: Add a command to show virtual memory mappings
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 13/48] riscv: sifive_test: Add reset functionality
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 11/48] riscv: Resolve full path of the given bios image
,
Palmer Dabbelt
,
11:28
[Qemu-riscv] [PULL 09/48] riscv: rv32: Root page table address can be larger than 32-bit
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 08/48] target/riscv: Update the Hypervisor CSRs to v0.4
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 07/48] target/riscv: Create function to test if FP is enabled
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 06/48] riscv: plic: Remove unused interrupt functions
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 05/48] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 04/48] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 03/48] riscv: sifive_u: Fix clock-names property for ethernet node
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 02/48] riscv: sivive_u: Add dummy serial clock and aliases entry for uart
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3
,
Palmer Dabbelt
,
11:27
[Qemu-riscv] [PULL 01/48] riscv: sifive_u: Add support for loading initrd
,
Palmer Dabbelt
,
11:27
September 17, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook
,
Richard Henderson
,
22:15
Re: [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Jonathan Behrens
,
22:00
Re: [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Alistair Francis
,
19:37
[Qemu-riscv] [PATCH v1 2/2] RISC-V: Implement cpu_do_transaction_failed
,
Alistair Francis
,
19:27
[Qemu-riscv] [PATCH v1 1/2] RISC-V: Handle bus errors in the page table walker
,
Alistair Francis
,
19:27
[Qemu-riscv] [PATCH v1 0/2] RISC-V: Convert to do_transaction_failed hook
,
Alistair Francis
,
19:27
Re: [Qemu-riscv] [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Alistair Francis
,
12:42
Re: [Qemu-riscv] [Qemu-devel] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access
,
Peter Maydell
,
09:56
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
liuzhiwei
,
04:19
September 16, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers
,
Alistair Francis
,
17:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Alistair Francis
,
13:07
Re: [Qemu-riscv] [PATCH v1 02/28] target/riscv: Add the virtulisation mode
,
Alistair Francis
,
12:02
[Qemu-riscv] [PATCH v1 1/1] riscv: pmp: Allow valid instruction fetches at the start of a PMP range
,
Chris Williams
,
05:08
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
03:51
September 15, 2019
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Palmer Dabbelt
,
18:16
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Jonathan Behrens
,
13:40
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Palmer Dabbelt
,
13:31
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
09:07
September 14, 2019
Re: [Qemu-riscv] [PATCH v1 15/28] riscv: plic: Always set sip.SEIP bit for HS
,
Palmer Dabbelt
,
16:33
Re: [Qemu-riscv] [PATCH v1 14/28] target/riscv: Generate illegal instruction on WFI when V=1
,
Palmer Dabbelt
,
16:30
Re: [Qemu-riscv] [PATCH v1 13/28] target/ricsv: Flush the TLB on virtulisation mode changes
,
Palmer Dabbelt
,
16:30
Re: [Qemu-riscv] [PATCH v1 12/28] target/riscv: Add support for virtual interrupt setting
,
Palmer Dabbelt
,
16:30
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Palmer Dabbelt
,
15:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH v1 2/4] elf: move elf.h to elf/elf.h and split out types
,
Richard Henderson
,
14:16
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr
,
Palmer Dabbelt
,
09:58
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension
,
Palmer Dabbelt
,
08:59
September 13, 2019
Re: [Qemu-riscv] [PATCH v1] gdbstub: riscv: fix the fflags registers
,
Palmer Dabbelt
,
17:20
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
11:25
Re: [Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Palmer Dabbelt
,
10:33
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1
,
Palmer Dabbelt
,
10:17
Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1
,
Peter Maydell
,
05:17
September 12, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 17/17] RISC-V: add vector extension premutation instructions
,
Richard Henderson
,
13:13
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 16/17] RISC-V: add vector extension mask instructions
,
Richard Henderson
,
13:07
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions
,
Richard Henderson
,
12:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 09/17] RISC-V: add vector extension integer instructions part2, bit/shift
,
Richard Henderson
,
12:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc
,
Richard Henderson
,
11:35
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc
,
Richard Henderson
,
11:27
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
Richard Henderson
,
11:06
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions
,
Richard Henderson
,
10:57
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
Chih-Min Chao
,
10:54
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation
,
Richard Henderson
,
10:32
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions
,
Richard Henderson
,
10:23
September 11, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 04/17] RISC-V: add vector extension configure instruction
,
Richard Henderson
,
19:09
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 03/17] RISC-V: support vector extension csr
,
Richard Henderson
,
18:43
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
Richard Henderson
,
18:39
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
Richard Henderson
,
18:32
Re: [Qemu-riscv] [PATCH v2 04/17] RISC-V: add vector extension configure instruction
,
Chih-Min Chao
,
12:05
Re: [Qemu-riscv] [PATCH v2 03/17] RISC-V: support vector extension csr
,
Chih-Min Chao
,
11:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property
,
Chih-Min Chao
,
11:00
Re: [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Jonathan Behrens
,
10:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
Chih-Min Chao
,
10:51
Re: [Qemu-riscv] [PATCH v1 11/28] target/riscv: Add background register swapping function
,
Palmer Dabbelt
,
10:17
Re: [Qemu-riscv] [PATCH v1 2/4] elf: move elf.h to elf/elf.h and split out types
,
Alex Bennée
,
05:19
Re: [Qemu-riscv] [PATCH v1 2/4] elf: move elf.h to elf/elf.h and split out types
,
BALATON Zoltan
,
04:30
[Qemu-riscv] [PULL 46/47] target/riscv: Fix mstatus dirty mask
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 45/47] target/riscv: Use both register name and ABI name
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 39/47] riscv: roms: Update default bios for sifive_u machine
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 42/47] riscv: sifive_u: Fix broken GEM support
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 32/47] riscv: sifive_u: Update PLIC hart topology configuration string
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 31/47] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 30/47] riscv: sifive_u: Set the minimum number of cpus to 2
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 28/47] riscv: hart: Extract hart realize to a separate routine
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 29/47] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 26/47] riscv: sifive_e: Drop sifive_mmio_emulate()
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 27/47] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 25/47] riscv: sifive_e: prci: Update the PRCI register block size
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 23/47] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 24/47] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 21/47] riscv: roms: Remove executable attribute of opensbi images
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 22/47] riscv: sifive_u: Remove the unnecessary include of prci header
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 20/47] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 19/47] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 18/47] riscv: hw: Change create_fdt() to return void
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 17/47] riscv: hw: Remove not needed PLIC properties in device tree
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 16/47] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 15/47] riscv: hw: Remove superfluous "linux, phandle" property
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 14/47] riscv: hw: Remove duplicated "hw/hw.h" inclusion
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 12/47] riscv: hmp: Add a command to show virtual memory mappings
,
Palmer Dabbelt
,
04:25
[Qemu-riscv] [PULL 13/47] riscv: sifive_test: Add reset functionality
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 11/47] riscv: Resolve full path of the given bios image
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 10/47] riscv: Add a helper routine for finding firmware
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 09/47] riscv: rv32: Root page table address can be larger than 32-bit
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 08/47] target/riscv: Update the Hypervisor CSRs to v0.4
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 07/47] target/riscv: Create function to test if FP is enabled
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 06/47] riscv: plic: Remove unused interrupt functions
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 05/47] target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 04/47] target/riscv/pmp: Restrict priviledged PMP to system-mode emulation
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 03/47] riscv: sifive_u: Fix clock-names property for ethernet node
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 02/47] riscv: sivive_u: Add dummy serial clock and aliases entry for uart
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL 01/47] riscv: sifive_u: Add support for loading initrd
,
Palmer Dabbelt
,
04:24
Re: [Qemu-riscv] [PATCH v1 10/28] target/riscv: Convert mie and mstatus to pointers
,
Palmer Dabbelt
,
04:24
[Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1
,
Palmer Dabbelt
,
04:24
Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 00/17] RISC-V: support vector extension
,
Aleksandar Markovic
,
03:01
[Qemu-riscv] [PATCH v2 11/17] RISC-V: add vector extension integer instructions part4, mul/div/merge
,
liuzhiwei
,
02:36
[Qemu-riscv] [PATCH v2 14/17] RISC-V: add vector extension float instructions part2, sqrt/cmp/cvt/others
,
liuzhiwei
,
02:36
[Qemu-riscv] [PATCH v2 12/17] RISC-V: add vector extension fixed point instructions
,
liuzhiwei
,
02:36
[Qemu-riscv] [PATCH v2 13/17] RISC-V: add vector extension float instruction part1, add/sub/mul/div
,
liuzhiwei
,
02:36
[Qemu-riscv] [PATCH v2 15/17] RISC-V: add vector extension reduction instructions
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 17/17] RISC-V: add vector extension premutation instructions
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 16/17] RISC-V: add vector extension mask instructions
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 08/17] RISC-V: add vector extension integer instructions part1, add/sub/adc/sbc
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 05/17] RISC-V: add vector extension load and store instructions
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 10/17] RISC-V: add vector extension integer instructions part3, cmp/min/max
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 09/17] RISC-V: add vector extension integer instructions part2, bit/shift
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 07/17] RISC-V: add vector extension atomic instructions
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 06/17] RISC-V: add vector extension fault-only-first implementation
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 04/17] RISC-V: add vector extension configure instruction
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 00/17] RISC-V: support vector extension
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 02/17] RISC-V: turn on vector extension from command line by cfg.ext_v Property
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 03/17] RISC-V: support vector extension csr
,
liuzhiwei
,
02:35
[Qemu-riscv] [PATCH v2 01/17] RISC-V: add vfp field in CPURISCVState
,
liuzhiwei
,
02:35
September 10, 2019
Re: [Qemu-riscv] [PATCH v1 2/4] elf: move elf.h to elf/elf.h and split out types
,
David Gibson
,
20:32
[Qemu-riscv] [PATCH v1 2/4] elf: move elf.h to elf/elf.h and split out types
,
Alex Bennée
,
15:34
Re: [Qemu-riscv] [PATCH v1 09/28] target/riscv: Add Hypervisor virtual CSRs accesses
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 08/28] target/riscv: Add Hypervisor CSR access functions
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 07/28] target/riscv: Dump Hypervisor registers if enabled
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 06/28] target/riscv: Print priv and virt in disas log
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 04/28] target/riscv: Fix CSR perm checking for HS mode
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 03/28] target/riscv: Add the force HS exception mode
,
Palmer Dabbelt
,
10:48
Re: [Qemu-riscv] [PATCH v1 02/28] target/riscv: Add the virtulisation mode
,
Palmer Dabbelt
,
09:44
Re: [Qemu-riscv] [PATCH v1 01/28] target/riscv: Add the Hypervisor extension
,
Palmer Dabbelt
,
09:44
Re: [Qemu-riscv] [PATCH v4 0/7] RISC-V: Hypervisor prep work part 2
,
Palmer Dabbelt
,
09:16
Re: [Qemu-riscv] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point
,
Palmer Dabbelt
,
09:16
[Qemu-riscv] ANNOUNCE: emails from this mailing list will soon drop the [qemu-*] subject tag
,
Peter Maydell
,
04:38
[Qemu-riscv] [PATCH v1] gdbstub: riscv: fix the fflags registers
,
KONRAD Frederic
,
04:16
September 09, 2019
Re: [Qemu-riscv] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540
,
Palmer Dabbelt
,
12:21
Re: [Qemu-riscv] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion
,
Palmer Dabbelt
,
12:21
September 06, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion
,
Alistair Francis
,
17:25
Re: [Qemu-riscv] [Qemu-devel] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images
,
Philippe Mathieu-Daudé
,
12:25
[Qemu-riscv] [PATCH v8 27/32] riscv: roms: Update default bios for sifive_u machine
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 30/32] riscv: sifive_u: Fix broken GEM support
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 28/32] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 31/32] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 32/32] riscv: sifive_u: Update model and compatible strings in device tree
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 29/32] riscv: sifive_u: Instantiate OTP memory with a serial number
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 19/32] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 21/32] riscv: sifive: Implement PRCI model for FU540
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 25/32] riscv: sifive_u: Update UART base addresses and IRQs
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 24/32] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 26/32] riscv: sifive_u: Change UART node name in device tree
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 23/32] riscv: sifive_u: Add PRCI block to the SoC
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 20/32] riscv: sifive_u: Update PLIC hart topology configuration string
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 18/32] riscv: sifive_u: Set the minimum number of cpus to 2
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 22/32] riscv: sifive_u: Generate hfclk and rtcclk nodes
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Bin Meng
,
12:21
[Qemu-riscv] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate()
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 00/32] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 03/32] riscv: hw: Remove superfluous "linux, phandle" property
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 02/32] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
12:20
[Qemu-riscv] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion
,
Bin Meng
,
12:20
September 05, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
20:33
Re: [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
,
Palmer Dabbelt
,
15:17
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Palmer Dabbelt
,
15:00
Re: [Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
11:58
[Qemu-riscv] [PATCH v2] riscv: sifive_test: Add reset functionality
,
Bin Meng
,
11:55
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Bin Meng
,
11:26
September 04, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 00/30] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine
,
Alistair Francis
,
15:50
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Palmer Dabbelt
,
14:34
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 26/30] riscv: sifive: Implement a model for SiFive FU540 OTP
,
Alistair Francis
,
12:37
September 03, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] riscv: sifive_e: Correct various SoC IP block sizes
,
Bin Meng
,
23:42
Re: [Qemu-riscv] [Qemu-devel] [PATCH v7 15/30] riscv: hart: Add a "hartid-base" property to RISC-V hart array
,
Alistair Francis
,
19:09
Re: [Qemu-riscv] [PATCH v4] riscv: hmp: Add a command to show virtual memory mappings
,
Palmer Dabbelt
,
14:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
10:46
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
Richard Henderson
,
10:38
September 02, 2019
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
05:49
Re: [Qemu-riscv] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
04:23
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
03:51
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
03:00
Re: [Qemu-riscv] [Qemu-devel] [PATCH] RISCV: support riscv vector extension 0.7.1
,
liuzhiwei
,
02:42
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