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[PATCH v1 26/36] target/riscv: Remove the hret instruction
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From: |
Alistair Francis |
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Subject: |
[PATCH v1 26/36] target/riscv: Remove the hret instruction |
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Date: |
Mon, 9 Dec 2019 10:11:48 -0800 |
The hret instruction does not exist in the new spec versions, so remove
it from QEMU.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/insn32.decode | 1 -
target/riscv/insn_trans/trans_privileged.inc.c | 5 -----
2 files changed, 6 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index cfd9ca6d2b..b883672e63 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -75,7 +75,6 @@ ecall 000000000000 00000 000 00000 1110011
ebreak 000000000001 00000 000 00000 1110011
uret 0000000 00010 00000 000 00000 1110011
sret 0001000 00010 00000 000 00000 1110011
-hret 0010000 00010 00000 000 00000 1110011
mret 0011000 00010 00000 000 00000 1110011
wfi 0001000 00101 00000 000 00000 1110011
hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
diff --git a/target/riscv/insn_trans/trans_privileged.inc.c
b/target/riscv/insn_trans/trans_privileged.inc.c
index b9b5a89b52..76c2fad71c 100644
--- a/target/riscv/insn_trans/trans_privileged.inc.c
+++ b/target/riscv/insn_trans/trans_privileged.inc.c
@@ -58,11 +58,6 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
#endif
}
-static bool trans_hret(DisasContext *ctx, arg_hret *a)
-{
- return false;
-}
-
static bool trans_mret(DisasContext *ctx, arg_mret *a)
{
#ifndef CONFIG_USER_ONLY
--
2.24.0
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension, (continued)
- [PATCH v1 17/36] target/riscv: Set VS bits in mideleg for Hyp extension, Alistair Francis, 2019/12/09
- [PATCH v1 15/36] target/riscv: Convert mstatus to pointers, Alistair Francis, 2019/12/09
- [PATCH v1 18/36] target/riscv: Extend the MIE CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 19/36] target/riscv: Extend the SIP CSR to support virtulisation, Alistair Francis, 2019/12/09
- [PATCH v1 20/36] target/riscv: Add support for virtual interrupt setting, Alistair Francis, 2019/12/09
- [PATCH v1 21/36] target/ricsv: Flush the TLB on virtulisation mode changes, Alistair Francis, 2019/12/09
- [PATCH v1 22/36] target/riscv: Generate illegal instruction on WFI when V=1, Alistair Francis, 2019/12/09
- [PATCH v1 23/36] target/riscv: Add hypvervisor trap support, Alistair Francis, 2019/12/09
- [PATCH v1 24/36] target/riscv: Add Hypervisor trap return support, Alistair Francis, 2019/12/09
- [PATCH v1 25/36] target/riscv: Add hfence instructions, Alistair Francis, 2019/12/09
- [PATCH v1 26/36] target/riscv: Remove the hret instruction,
Alistair Francis <=
- [PATCH v1 28/36] target/riscv: Mark both sstatus and vsstatus as dirty, Alistair Francis, 2019/12/09
- [PATCH v1 27/36] target/riscv: Disable guest FP support based on virtual status, Alistair Francis, 2019/12/09
- [PATCH v1 29/36] target/riscv: Respect MPRV and SPRV for floating point ops, Alistair Francis, 2019/12/09
- [PATCH v1 30/36] target/riscv: Allow specifying MMU stage, Alistair Francis, 2019/12/09
- [PATCH v1 32/36] target/riscv: Raise the new execptions when 2nd stage translation fails, Alistair Francis, 2019/12/09
- [PATCH v1 31/36] target/riscv: Implement second stage MMU, Alistair Francis, 2019/12/09
- [PATCH v1 33/36] target/riscv: Set htval and mtval2 on execptions, Alistair Francis, 2019/12/09
- [PATCH v1 34/36] target/riscv: Add support for the 32-bit MSTATUSH CSR, Alistair Francis, 2019/12/09
- [PATCH v1 35/36] target/riscv: Add the MSTATUS_MPV_ISSET helper macro, Alistair Francis, 2019/12/09
- [PATCH v1 36/36] target/riscv: Allow enabling the Hypervisor extension, Alistair Francis, 2019/12/09