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[PATCH v10 02/61] target/riscv: implementation-defined constant paramete
From: |
LIU Zhiwei |
Subject: |
[PATCH v10 02/61] target/riscv: implementation-defined constant parameters |
Date: |
Sat, 20 Jun 2020 12:36:02 +0800 |
vlen is the vector register length in bits.
elen is the max element size in bits.
vext_spec is the vector specification version, default value is v0.7.1.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/cpu.c | 7 +++++++
target/riscv/cpu.h | 5 +++++
2 files changed, 12 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 391a0b9eec..d525cfb687 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -106,6 +106,11 @@ static void set_priv_version(CPURISCVState *env, int
priv_ver)
env->priv_ver = priv_ver;
}
+static void set_vext_version(CPURISCVState *env, int vext_ver)
+{
+ env->vext_ver = vext_ver;
+}
+
static void set_feature(CPURISCVState *env, int feature)
{
env->features |= (1ULL << feature);
@@ -334,6 +339,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
CPURISCVState *env = &cpu->env;
RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
int priv_version = PRIV_VERSION_1_11_0;
+ int vext_version = VEXT_VERSION_0_07_1;
target_ulong target_misa = 0;
Error *local_err = NULL;
@@ -357,6 +363,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
set_priv_version(env, priv_version);
+ set_vext_version(env, vext_version);
if (cpu->cfg.mmu) {
set_feature(env, RISCV_FEATURE_MMU);
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 0018a79fa3..302e0859a0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -78,6 +78,8 @@ enum {
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
+#define VEXT_VERSION_0_07_1 0x00000701
+
#define TRANSLATE_PMP_FAIL 2
#define TRANSLATE_FAIL 1
#define TRANSLATE_SUCCESS 0
@@ -113,6 +115,7 @@ struct CPURISCVState {
target_ulong guest_phys_fault_addr;
target_ulong priv_ver;
+ target_ulong vext_ver;
target_ulong misa;
target_ulong misa_mask;
@@ -275,6 +278,8 @@ typedef struct RISCVCPU {
char *priv_spec;
char *user_spec;
+ uint16_t vlen;
+ uint16_t elen;
bool mmu;
bool pmp;
} cfg;
--
2.23.0
- [PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions, (continued)
- [PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions, LIU Zhiwei, 2020/06/19
- [PATCH v10 31/61] target/riscv: vector widening floating-point add/subtract instructions, LIU Zhiwei, 2020/06/19
- [PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 33/61] target/riscv: vector widening floating-point multiply, LIU Zhiwei, 2020/06/20
- [PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 35/61] target/riscv: vector widening floating-point fused multiply-add instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 36/61] target/riscv: vector floating-point square-root instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 37/61] target/riscv: vector floating-point min/max instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 00/61] target/riscv: support vector extension v0.7.1, LIU Zhiwei, 2020/06/20
- [PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState, LIU Zhiwei, 2020/06/20
- [PATCH v10 02/61] target/riscv: implementation-defined constant parameters,
LIU Zhiwei <=
- [PATCH v10 03/61] target/riscv: support vector extension csr, LIU Zhiwei, 2020/06/20
- [PATCH v10 04/61] target/riscv: add vector configure instruction, LIU Zhiwei, 2020/06/20
- [PATCH v10 05/61] target/riscv: add an internals.h header, LIU Zhiwei, 2020/06/20
- [PATCH v10 06/61] target/riscv: add vector stride load and store instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 07/61] target/riscv: add vector index load and store instructions, LIU Zhiwei, 2020/06/20
- [PATCH v10 08/61] target/riscv: add fault-only-first unit stride load, LIU Zhiwei, 2020/06/20
- [PATCH v10 09/61] target/riscv: add vector amo operations, LIU Zhiwei, 2020/06/20
- [PATCH v10 10/61] target/riscv: vector single-width integer add and subtract, LIU Zhiwei, 2020/06/20