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Re: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU |
Date: |
Fri, 2 Apr 2021 09:04:04 -0400 |
On Thu, Apr 1, 2021 at 2:15 PM Vijai Kumar K <vijai@behindbytes.com> wrote:
>
> C-Class is a member of the SHAKTI family of processors from IIT-M.
>
> It is an extremely configurable and commercial-grade 5-stage in-order
> core supporting the standard RV64GCSUN ISA extensions.
>
> Signed-off-by: Vijai Kumar K <vijai@behindbytes.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 1 +
> target/riscv/cpu.h | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 2a990f6253..140094fd52 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -707,6 +707,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init),
> DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init),
> + DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init),
> #endif
> };
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 0edb2826a2..ebbf15fb1c 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -38,6 +38,7 @@
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
> +#define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c")
> #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
> #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
> #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
> --
> 2.25.1
>
>
- [PATCH v3 0/4] Add support for Shakti SoC from IIT-M, Vijai Kumar K, 2021/04/01
- [PATCH v3 1/4] target/riscv: Add Shakti C class CPU, Vijai Kumar K, 2021/04/01
- Re: [PATCH v3 1/4] target/riscv: Add Shakti C class CPU,
Alistair Francis <=
- [PATCH v3 4/4] hw/riscv: Connect Shakti UART to Shakti platform, Vijai Kumar K, 2021/04/01
- [PATCH v3 2/4] riscv: Add initial support for Shakti C machine, Vijai Kumar K, 2021/04/01
- [PATCH v3 3/4] hw/char: Add Shakti UART emulation, Vijai Kumar K, 2021/04/01
- Re: [PATCH v3 0/4] Add support for Shakti SoC from IIT-M, Alistair Francis, 2021/04/02