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[RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode
From: |
LIU Zhiwei |
Subject: |
[RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode |
Date: |
Fri, 9 Apr 2021 15:48:52 +0800 |
The new CLIC interrupt-handling mode is encoded as a new state in the
existing WARL xtvec register, where the low two bits of are 11.
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
target/riscv/csr.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f6c84b9fe4..39ff72041a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -637,9 +637,18 @@ static int read_mtvec(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
{
- /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ /*
+ * bits [1:0] encode mode; 0 = direct, 1 = vectored, 3 = CLIC,
+ * others reserved
+ */
if ((val & 3) < 2) {
env->mtvec = val;
+ } else if ((val & 1) && env->clic) {
+ /*
+ * If only CLIC mode is supported, writes to bit 1 are also ignored and
+ * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to zero.
+ */
+ env->mtvec = ((val & ~0x3f) << 6) | (0b000011);
} else {
qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
}
@@ -837,9 +846,18 @@ static int read_stvec(CPURISCVState *env, int csrno,
target_ulong *val)
static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
{
- /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
+ /*
+ * bits [1:0] encode mode; 0 = direct, 1 = vectored, 3 = CLIC,
+ * others reserved
+ */
if ((val & 3) < 2) {
env->stvec = val;
+ } else if ((val & 1) && env->clic) {
+ /*
+ * If only CLIC mode is supported, writes to bit 1 are also ignored and
+ * it is always set to one. CLIC mode hardwires xtvec bits 2-5 to zero.
+ */
+ env->stvec = ((val & ~0x3f) << 6) | (0b000011);
} else {
qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
}
--
2.25.1
- [RFC PATCH 00/11] RISC-V: support clic v0.9 specification, LIU Zhiwei, 2021/04/09
- [RFC PATCH 04/11] target/riscv: Update CSR xie in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 01/11] target/riscv: Add CLIC CSR mintstatus, LIU Zhiwei, 2021/04/09
- [RFC PATCH 08/11] target/riscv: Update CSR xnxti in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 05/11] target/riscv: Update CSR xip in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 09/11] target/riscv: Update CSR mclicbase in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 06/11] target/riscv: Update CSR xtvec in CLIC mode,
LIU Zhiwei <=
- [RFC PATCH 07/11] target/riscv: Update CSR xtvt in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 10/11] target/riscv: Update interrupt handling in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 11/11] target/riscv: Update interrupt return in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 02/11] target/riscv: Update CSR xintthresh in CLIC mode, LIU Zhiwei, 2021/04/09
- [RFC PATCH 03/11] hw/intc: Add CLIC device, LIU Zhiwei, 2021/04/09
- Re: [RFC PATCH 00/11] RISC-V: support clic v0.9 specification, Alistair Francis, 2021/04/19