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[PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM whe
From: |
Yifei Jiang |
Subject: |
[PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled |
Date: |
Mon, 12 Apr 2021 14:52:41 +0800 |
Only support supervisor external interrupt currently.
Signed-off-by: Yifei Jiang <jiangyifei@huawei.com>
Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com>
---
hw/intc/sifive_plic.c | 29 ++++++++++++++++++++---------
target/riscv/kvm-stub.c | 5 +++++
target/riscv/kvm.c | 20 ++++++++++++++++++++
target/riscv/kvm_riscv.h | 1 +
4 files changed, 46 insertions(+), 9 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index 97a1a27a9a..2746eb7a05 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,6 +31,8 @@
#include "target/riscv/cpu.h"
#include "sysemu/sysemu.h"
#include "migration/vmstate.h"
+#include "sysemu/kvm.h"
+#include "kvm_riscv.h"
#define RISCV_DEBUG_PLIC 0
@@ -147,15 +149,24 @@ static void sifive_plic_update(SiFivePLICState *plic)
continue;
}
int level = sifive_plic_irqs_pending(plic, addrid);
- switch (mode) {
- case PLICMode_M:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP,
BOOL_TO_MASK(level));
- break;
- case PLICMode_S:
- riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP,
BOOL_TO_MASK(level));
- break;
- default:
- break;
+ if (kvm_enabled()) {
+ if (mode == PLICMode_M) {
+ continue;
+ }
+ kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level);
+ } else {
+ switch (mode) {
+ case PLICMode_M:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_MEIP, BOOL_TO_MASK(level));
+ break;
+ case PLICMode_S:
+ riscv_cpu_update_mip(RISCV_CPU(cpu),
+ MIP_SEIP, BOOL_TO_MASK(level));
+ break;
+ default:
+ break;
+ }
}
}
diff --git a/target/riscv/kvm-stub.c b/target/riscv/kvm-stub.c
index 39b96fe3f4..4e8fc31a21 100644
--- a/target/riscv/kvm-stub.c
+++ b/target/riscv/kvm-stub.c
@@ -23,3 +23,8 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
{
abort();
}
+
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ abort();
+}
diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c
index 79c931acb4..da63535812 100644
--- a/target/riscv/kvm.c
+++ b/target/riscv/kvm.c
@@ -453,6 +453,26 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu)
env->gpr[11] = cpu->env.fdt_addr; /* a1 */
}
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level)
+{
+ int ret;
+ unsigned virq = level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET;
+
+ if (irq != IRQ_S_EXT) {
+ return;
+ }
+
+ if (!kvm_enabled()) {
+ return;
+ }
+
+ ret = kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq);
+ if (ret < 0) {
+ perror("Set irq failed");
+ abort();
+ }
+}
+
bool kvm_arch_cpu_check_are_resettable(void)
{
return true;
diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h
index f38c82bf59..ed281bdce0 100644
--- a/target/riscv/kvm_riscv.h
+++ b/target/riscv/kvm_riscv.h
@@ -20,5 +20,6 @@
#define QEMU_KVM_RISCV_H
void kvm_riscv_reset_vcpu(RISCVCPU *cpu);
+void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level);
#endif
--
2.19.1
- [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM, (continued)
- [PATCH RFC v5 06/12] target/riscv: Support start kernel directly by KVM, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 03/12] target/riscv: Implement function kvm_arch_init_vcpu, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 02/12] target/riscv: Add target/riscv/kvm.c to place the public kvm interface, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 05/12] target/riscv: Implement kvm_arch_put_registers, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 04/12] target/riscv: Implement kvm_arch_get_registers, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 08/12] target/riscv: Handle KVM_EXIT_RISCV_SBI exit, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 07/12] hw/riscv: PLIC update external interrupt by KVM when kvm enabled,
Yifei Jiang <=
- [PATCH RFC v5 11/12] target/riscv: Implement virtual time adjusting with vm state changing, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 10/12] target/riscv: Add kvm_riscv_get/put_regs_timer, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 09/12] target/riscv: Add host cpu type, Yifei Jiang, 2021/04/12
- [PATCH RFC v5 12/12] target/riscv: Support virtual time context synchronization, Yifei Jiang, 2021/04/12