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[PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro
From: |
Alistair Francis |
Subject: |
[PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro |
Date: |
Wed, 14 Apr 2021 09:33:49 +1000 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_bits.h | 10 ----------
target/riscv/csr.c | 12 ++++++++++--
target/riscv/translate.c | 20 ++++++++++++++++++--
3 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 8caab23b62..dd643d0f63 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -387,16 +387,6 @@
#define MXL_RV64 2
#define MXL_RV128 3
-#if defined(TARGET_RISCV32)
-#define MSTATUS_SD MSTATUS32_SD
-#define MISA_MXL MISA32_MXL
-#define MXL_VAL MXL_RV32
-#elif defined(TARGET_RISCV64)
-#define MSTATUS_SD MSTATUS64_SD
-#define MISA_MXL MISA64_MXL
-#define MXL_VAL MXL_RV64
-#endif
-
/* sstatus CSR bits */
#define SSTATUS_UIE 0x00000001
#define SSTATUS_SIE 0x00000002
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 832c3bf7fd..6052b2d6e9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -492,7 +492,11 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
((mstatus & MSTATUS_XS) == MSTATUS_XS);
- mstatus = set_field(mstatus, MSTATUS_SD, dirty);
+ if (riscv_cpu_is_32bit(env)) {
+ mstatus = set_field(mstatus, MSTATUS32_SD, dirty);
+ } else {
+ mstatus = set_field(mstatus, MSTATUS64_SD, dirty);
+ }
env->mstatus = mstatus;
return 0;
@@ -564,7 +568,11 @@ static int write_misa(CPURISCVState *env, int csrno,
target_ulong val)
}
/* misa.MXL writes are not supported by QEMU */
- val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
+ if (riscv_cpu_is_32bit(env)) {
+ val = (env->misa & MISA32_MXL) | (val & ~MISA32_MXL);
+ } else {
+ val = (env->misa & MISA64_MXL) | (val & ~MISA64_MXL);
+ }
/* flush translation cache */
if (val != env->misa) {
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 2f9f5ccc62..74636b9db7 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -78,6 +78,17 @@ static inline bool has_ext(DisasContext *ctx, uint32_t ext)
return ctx->misa & ext;
}
+#ifndef CONFIG_USER_ONLY
+# ifdef TARGET_RISCV32
+# define is_32bit(ctx) true
+# else
+static inline bool is_32bit(DisasContext *ctx)
+{
+ return !(ctx->misa & RV64);
+}
+# endif
+#endif
+
/*
* RISC-V requires NaN-boxing of narrower width floating point values.
* This applies when a 32-bit value is assigned to a 64-bit FP register.
@@ -369,6 +380,8 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
static void mark_fs_dirty(DisasContext *ctx)
{
TCGv tmp;
+ target_ulong sd;
+
if (ctx->mstatus_fs == MSTATUS_FS) {
return;
}
@@ -376,13 +389,16 @@ static void mark_fs_dirty(DisasContext *ctx)
ctx->mstatus_fs = MSTATUS_FS;
tmp = tcg_temp_new();
+ sd = is_32bit(ctx) ? MSTATUS32_SD : MSTATUS64_SD;
+
+
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
if (ctx->virt_enabled) {
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
- tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | MSTATUS_SD);
+ tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS | sd);
tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus_hs));
}
tcg_temp_free(tmp);
--
2.31.1
- [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro, (continued)
- [PATCH v2 5/9] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/04/13
- [PATCH v2 6/9] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/04/13
- [PATCH v2 8/9] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/04/13
- [PATCH v2 7/9] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/04/13
- [PATCH v2 4/9] target/riscv: Remove the hardcoded MSTATUS_SD macro,
Alistair Francis <=
- [PATCH v2 9/9] target/riscv: Consolidate RV32/64 16-bit instructions, Alistair Francis, 2021/04/13