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[PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on
From: |
Alistair Francis |
Subject: |
[PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on |
Date: |
Sat, 24 Apr 2021 13:28:20 +1000 |
This is another step towards running 32-bit CPU code on the 64-bit
softmmu builds for RISC-V.
I have tested this and am able to run some 32-bit code, but eventually
hit some issue. This series doesn't allow users to use 32-bit CPUs with
64-bit softmmu builds as it doesn't work yet. This series instead just
gets us a little closer to being able to and removes more hardcoded
macros so hopefully others also stop using them for new code.
v3:
- Remove casts from the decoder
- Add a patch to fix a comment
- Rebase on the RISC-V tree
v2:
- Update the decode tree setup
- Address other review comments
Alistair Francis (10):
target/riscv: Remove the hardcoded RVXLEN macro
target/riscv: Remove the hardcoded SSTATUS_SD macro
target/riscv: Remove the hardcoded HGATP_MODE macro
target/riscv: Remove the hardcoded MSTATUS_SD macro
target/riscv: Remove the hardcoded SATP_MODE macro
target/riscv: Remove the unused HSTATUS_WPRI macro
target/riscv: Remove an unused CASE_OP_32_64 macro
target/riscv: Consolidate RV32/64 32-bit instructions
target/riscv: Consolidate RV32/64 16-bit instructions
target/riscv: Fix the RV64H decode comment
target/riscv/cpu.h | 6 --
target/riscv/cpu_bits.h | 44 -------------
target/riscv/helper.h | 18 +++--
target/riscv/insn16-32.decode | 28 --------
target/riscv/insn16-64.decode | 36 ----------
target/riscv/insn16.decode | 30 +++++++++
target/riscv/insn32-64.decode | 88 -------------------------
target/riscv/insn32.decode | 67 ++++++++++++++++++-
target/riscv/cpu.c | 6 +-
target/riscv/cpu_helper.c | 48 ++++++++++----
target/riscv/csr.c | 40 +++++++++--
target/riscv/fpu_helper.c | 16 ++---
target/riscv/monitor.c | 22 +++++--
target/riscv/translate.c | 32 +++++----
target/riscv/vector_helper.c | 4 --
target/riscv/insn_trans/trans_rva.c.inc | 14 +++-
target/riscv/insn_trans/trans_rvd.c.inc | 17 ++++-
target/riscv/insn_trans/trans_rvf.c.inc | 6 +-
target/riscv/insn_trans/trans_rvh.c.inc | 8 ++-
target/riscv/insn_trans/trans_rvi.c.inc | 22 +++++--
target/riscv/insn_trans/trans_rvm.c.inc | 12 +++-
target/riscv/insn_trans/trans_rvv.c.inc | 39 +++++------
target/riscv/meson.build | 13 ++--
23 files changed, 310 insertions(+), 306 deletions(-)
delete mode 100644 target/riscv/insn16-32.decode
delete mode 100644 target/riscv/insn16-64.decode
delete mode 100644 target/riscv/insn32-64.decode
--
2.31.1
- [PATCH v3 00/10] RISC-V: Steps towards running 32-bit guests on,
Alistair Francis <=
- [PATCH v3 01/10] target/riscv: Remove the hardcoded RVXLEN macro, Alistair Francis, 2021/04/23
- [PATCH v3 02/10] target/riscv: Remove the hardcoded SSTATUS_SD macro, Alistair Francis, 2021/04/23
- [PATCH v3 03/10] target/riscv: Remove the hardcoded HGATP_MODE macro, Alistair Francis, 2021/04/23
- [PATCH v3 04/10] target/riscv: Remove the hardcoded MSTATUS_SD macro, Alistair Francis, 2021/04/23
- [PATCH v3 05/10] target/riscv: Remove the hardcoded SATP_MODE macro, Alistair Francis, 2021/04/23
- [PATCH v3 06/10] target/riscv: Remove the unused HSTATUS_WPRI macro, Alistair Francis, 2021/04/23
- [PATCH v3 07/10] target/riscv: Remove an unused CASE_OP_32_64 macro, Alistair Francis, 2021/04/23
- [PATCH v3 08/10] target/riscv: Consolidate RV32/64 32-bit instructions, Alistair Francis, 2021/04/23