[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rm
From: |
Anup Patel |
Subject: |
[PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback |
Date: |
Thu, 2 Sep 2021 16:55:06 +0530 |
The AIA device emulation (such as AIA IMSIC) should be able to set
(or provide) AIA ireg read-modify-write callback for each privilege
level of a RISC-V HART.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/cpu.h | 19 +++++++++++++++++++
target/riscv/cpu_helper.c | 14 ++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 2cde2df7be..c5cdd26de4 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -239,6 +239,18 @@ struct CPURISCVState {
uint64_t (*rdtime_fn)(uint32_t);
uint32_t rdtime_fn_arg;
+ /* machine specific AIA ireg read-modify-write callback */
+#define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein) \
+ ((((__vgein) & 0x3f) << 24) | (((__virt) & 0x1) << 20) | \
+ (((__priv) & 0x3) << 16) | (__isel & 0xffff))
+#define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff)
+#define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3)
+#define AIA_IREG_VIRT(__ireg) (((__ireg) >> 20) & 0x1)
+#define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 24) & 0x3f)
+ int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg,
+ target_ulong *val, target_ulong new_val, target_ulong write_mask);
+ void *aia_ireg_rmw_fn_arg[4];
+
/* True if in debugger mode. */
bool debugger;
#endif
@@ -379,6 +391,13 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t
mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t),
uint32_t arg);
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+ int (*rmw_fn)(void *arg,
+ target_ulong reg,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong write_mask),
+ void *rmw_fn_arg);
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index ee316db594..fcc8bbd1b3 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -288,6 +288,20 @@ void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t
(*fn)(uint32_t),
env->rdtime_fn_arg = arg;
}
+void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv,
+ int (*rmw_fn)(void *arg,
+ target_ulong reg,
+ target_ulong *val,
+ target_ulong new_val,
+ target_ulong write_mask),
+ void *rmw_fn_arg)
+{
+ if (priv <= PRV_M) {
+ env->aia_ireg_rmw_fn[priv] = rmw_fn;
+ env->aia_ireg_rmw_fn_arg[priv] = rmw_fn_arg;
+ }
+}
+
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {
--
2.25.1
- Re: [PATCH v2 04/22] target/riscv: Improve fidelity of guest external interrupts, (continued)
[PATCH v2 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/09/02
[PATCH v2 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/09/02
[PATCH v2 11/22] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/09/02
[PATCH v2 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/09/02
[PATCH v2 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback,
Anup Patel <=
[PATCH v2 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/09/02
[PATCH v2 10/22] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/09/02
[PATCH v2 12/22] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/09/02
[PATCH v2 13/22] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/09/02
[PATCH v2 14/22] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/09/02
[PATCH v2 15/22] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/09/02
[PATCH v2 16/22] hw/riscv: virt: Use AIA INTC compatible string when available, Anup Patel, 2021/09/02
[PATCH v2 17/22] target/riscv: Allow users to force enable AIA CSRs in HART, Anup Patel, 2021/09/02