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[PATCH v2 0/3] RISC-V: Populate mtval and stval
From: |
Alistair Francis |
Subject: |
[PATCH v2 0/3] RISC-V: Populate mtval and stval |
Date: |
Wed, 8 Sep 2021 14:54:13 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
Populate mtval and stval when taking an illegal instruction exception if
the features are set for the CPU.
Alistair Francis (3):
target/riscv: Set the opcode in DisasContext
target/riscv: Implement the stval/mtval illegal instruction
target/riscv: Set mtval and stval support
target/riscv/cpu.h | 6 +++++-
target/riscv/cpu.c | 6 +++++-
target/riscv/cpu_helper.c | 10 +++++++++
target/riscv/translate.c | 43 +++++++++++++++++++++------------------
4 files changed, 43 insertions(+), 22 deletions(-)
--
2.31.1
- [PATCH v2 0/3] RISC-V: Populate mtval and stval,
Alistair Francis <=
[PATCH v2 3/3] target/riscv: Set mtval and stval support, Alistair Francis, 2021/09/08