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[PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instruction
From: |
~eopxd |
Subject: |
[PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions |
Date: |
Mon, 25 Apr 2022 14:18:47 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 2 ++
target/riscv/vector_helper.c | 3 +++
2 files changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 4e141e5145..e2bdfc0fae 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1308,6 +1308,7 @@ static bool opivx_trans(uint32_t vd, uint32_t rs1,
uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
@@ -1484,6 +1485,7 @@ static bool opivi_trans(uint32_t vd, uint32_t imm,
uint32_t vs2, uint32_t vm,
data = FIELD_DP32(data, VDATA, VM, vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
desc = tcg_constant_i32(simd_desc(s->cfg_ptr->vlen / 8,
s->cfg_ptr->vlen / 8, data));
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index bd84b0409c..658ea0244d 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -891,10 +891,13 @@ static void do_vext_vx(void *vd, void *v0, target_long
s1, void *vs2,
uint32_t vl = env->vl;
uint32_t total_elems = vext_get_total_elems(desc, esz);
uint32_t vta = vext_vta(desc);
+ uint32_t vma = vext_vma(desc);
uint32_t i;
for (i = env->vstart; i < vl; i++) {
if (!vm && !vext_elem_mask(v0, i)) {
+ /* set masked-off elements to 1s */
+ vext_set_elems_1s_fns[ctzl(esz)](vd, vma, i, i * esz, (i + 1) *
esz);
continue;
}
fn(vd, s1, vs2, i);
--
2.34.2
- [PATCH qemu 0/9] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/04/25
- [PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions,
~eopxd <=
- [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/04/25
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, Weiwei Li, 2022/04/26
- Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, eop Chen, 2022/04/26
[PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/04/25
[PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/04/25
[PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/04/25