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[PATCH v8 03/12] target/riscv: pmu: Rename the counters extension to pmu
From: |
Atish Patra |
Subject: |
[PATCH v8 03/12] target/riscv: pmu: Rename the counters extension to pmu |
Date: |
Wed, 11 May 2022 14:59:47 -0700 |
From: Atish Patra <atish.patra@wdc.com>
The PMU counters are supported via cpu config "Counters" which doesn't
indicate the correct purpose of those counters.
Rename the config property to pmu to indicate that these counters
are performance monitoring counters. This aligns with cpu options for
ARM architecture as well.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
target/riscv/cpu.c | 2 +-
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ccacdee21575..5ad17b40189f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -822,7 +822,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false),
DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
- DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
+ DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe6c9a2c9238..09a0c71093c5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -391,7 +391,7 @@ struct RISCVCPUConfig {
bool ext_zksed;
bool ext_zksh;
bool ext_zkt;
- bool ext_counters;
+ bool ext_pmu;
bool ext_ifencei;
bool ext_icsr;
bool ext_svinval;
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d175fe3f1af3..c625b17dd58e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -74,8 +74,8 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
RISCVCPU *cpu = RISCV_CPU(cs);
int ctr_index;
- if (!cpu->cfg.ext_counters) {
- /* The Counters extensions is not enabled */
+ if (!cpu->cfg.ext_pmu) {
+ /* The PMU extension is not enabled */
return RISCV_EXCP_ILLEGAL_INST;
}
--
2.25.1
- [PATCH v8 00/12] Improve PMU support, Atish Patra, 2022/05/11
- [PATCH v8 01/12] target/riscv: Fix PMU CSR predicate function, Atish Patra, 2022/05/11
- [PATCH v8 02/12] target/riscv: Implement PMU CSR predicate function for S-mode, Atish Patra, 2022/05/11
- [PATCH v8 03/12] target/riscv: pmu: Rename the counters extension to pmu,
Atish Patra <=
- [PATCH v8 04/12] target/riscv: pmu: Make number of counters configurable, Atish Patra, 2022/05/11
- [PATCH v8 05/12] target/riscv: Implement mcountinhibit CSR, Atish Patra, 2022/05/11
- [PATCH v8 06/12] target/riscv: Add support for hpmcounters/hpmevents, Atish Patra, 2022/05/11
- [PATCH v8 08/12] target/riscv: Add sscofpmf extension support, Atish Patra, 2022/05/11
- [PATCH v8 07/12] target/riscv: Support mcycle/minstret write operation, Atish Patra, 2022/05/11
[PATCH v8 09/12] target/riscv: Simplify counter predicate function, Atish Patra, 2022/05/11