qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH] target/riscv: Remove condition guarding register zero for au


From: Richard Henderson
Subject: Re: [PATCH] target/riscv: Remove condition guarding register zero for auipc and lui
Date: Fri, 10 Jun 2022 11:11:13 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.9.1

On 6/10/22 09:55, Víctor Colombo wrote:
Commit 57c108b8646 introduced gen_set_gpri(), which already contains
a check for if the destination register is 'zero'. The check in auipc
and lui are then redundant. This patch removes those checks.

Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
---
  target/riscv/insn_trans/trans_rvi.c.inc | 8 ++------
  1 file changed, 2 insertions(+), 6 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~



reply via email to

[Prev in Thread] Current Thread [Next in Thread]