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qemu-riscv (date)
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Last Modified: Fri Sep 30 2022 17:57:41 -0400
Messages in reverse chronological order
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September 30, 2022
RE: [PATCH v6 16/18] hw/core: Add CPUClass.get_pc
,
Taylor Simpson
,
17:57
[PATCH v6 16/18] hw/core: Add CPUClass.get_pc
,
Richard Henderson
,
17:27
Re: [PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field
,
Jim Shu
,
09:09
Re: [PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field
,
Clément Chigot
,
08:58
[PATCH v2 2/2] hw/intc: sifive_plic: change interrupt priority register to WARL field
,
Jim Shu
,
08:33
[PATCH v2 1/2] hw/intc: sifive_plic: fix hard-coded max priority level
,
Jim Shu
,
08:32
[PATCH v2 0/2] Enhance maximum priority support of PLIC
,
Jim Shu
,
08:32
Re: [PATCH 3/6] riscv: re-randomize rng-seed on reboot
,
Bin Meng
,
05:11
September 29, 2022
[PATCH v5 2/2] hw/ssi: ibex_spi: fixup/add rw1c functionality
,
Wilfred Mallawa
,
23:34
[PATCH v5 1/2] hw/ssi: ibex_spi: fixup coverity issue
,
Wilfred Mallawa
,
23:33
[PATCH v5 0/2] hw/ssi/ibex_spi: bug fixes
,
Wilfred Mallawa
,
23:33
[RFC 5/8] target/riscv: add support for Zcmt extension
,
Weiwei Li
,
21:24
[RFC 1/8] target/riscv: add cfg properties for Zc* extension
,
Weiwei Li
,
21:24
[RFC 0/8] support subsets of code size reduction extension
,
Weiwei Li
,
21:24
[RFC 7/8] target/riscv: expose properties for Zc* extension
,
Weiwei Li
,
21:24
[RFC 8/8] disas/riscv.c: add disasm support for Zc*
,
Weiwei Li
,
21:24
[RFC 4/8] target/riscv: add support for Zcmp extension
,
Weiwei Li
,
21:24
[RFC 2/8] target/riscv: add support for Zca, Zcf and Zcd extension
,
Weiwei Li
,
21:24
[RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc
,
Weiwei Li
,
21:24
[RFC 3/8] target/riscv: add support for Zcb extension
,
Weiwei Li
,
21:24
[PATCH 3/6] riscv: re-randomize rng-seed on reboot
,
Jason A. Donenfeld
,
19:24
RE: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Dong, Eddie
,
14:11
Re: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Tyler Ng
,
12:02
September 28, 2022
Re: [PATCH v9 4/4] target/riscv: smstateen knobs
,
Alistair Francis
,
21:44
Re: [PATCH v9 1/4] target/riscv: Add smstateen support
,
Alistair Francis
,
21:43
Re: [PATCH v9 3/4] target/riscv: smstateen check for fcsr
,
weiwei
,
21:09
Re: [PATCH v9 1/4] target/riscv: Add smstateen support
,
weiwei
,
20:58
RE: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Dong, Eddie
,
19:00
RE: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Dong, Eddie
,
14:25
Re: [PATCH] hw/intc: sifive_plic: fix hard-coded max priority level
,
Jim Shu
,
11:53
Re: Re: [PATCH v2] disas/riscv.c: rvv: Add disas support for vector instructions
,
刘阳
,
01:22
[PATCH v3] disas/riscv.c: rvv: Add disas support for vector instructions
,
Yang Liu
,
01:19
[PATCH v1 2/2] riscv/opentitan: connect lifecycle controller
,
Wilfred Mallawa
,
01:10
[PATCH v1 1/2] hw/misc: add ibex lifecycle controller
,
Wilfred Mallawa
,
01:09
[PATCH v1 0/2] Add OpenTitan lifecycle controller
,
Wilfred Mallawa
,
01:09
September 27, 2022
Re: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Tyler Ng
,
20:13
RE: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Dong, Eddie
,
18:04
Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
,
Frank Chang
,
04:29
Re: [PATCH 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e
,
Frank Chang
,
03:28
Re: [PATCH 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.
,
Frank Chang
,
03:28
Re: [PATCH 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.
,
Frank Chang
,
03:27
Re: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Thomas Huth
,
02:31
September 26, 2022
Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Jim Shu
,
23:35
Re: [PATCH v2] disas/riscv.c: rvv: Add disas support for vector instructions
,
Alistair Francis
,
21:58
Re: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Tyler Ng
,
19:38
Re: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Tyler Ng
,
19:38
Re: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Tyler Ng
,
19:24
Re: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Tyler Ng
,
19:04
RE: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Dong, Eddie
,
17:09
RE: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Dong, Eddie
,
17:09
Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Tyler Ng
,
16:04
Re: [PATCH] hw/intc: sifive_plic: fix hard-coded max priority level
,
Clément Chigot
,
09:08
September 25, 2022
Re: [PATCH 2/2] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
,
Alistair Francis
,
17:18
Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Jim Shu
,
09:47
[PATCH] hw/intc: sifive_plic: fix hard-coded max priority level
,
Jim Shu
,
09:20
Re: [PATCH 2/2] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
,
Frank Chang
,
03:36
Re: [PATCH 1/2] target/riscv: rvv-1.0: Simplify vfwredsum code
,
Frank Chang
,
03:26
September 23, 2022
Re: [PATCH] include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState.
,
Alistair Francis
,
01:17
Re: [PATCH 2/2] target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered
,
Alistair Francis
,
00:58
Re: [PATCH 1/2] target/riscv: rvv-1.0: Simplify vfwredsum code
,
Alistair Francis
,
00:50
Re: [PATCH v2 0/8] target/riscv: Improve RISC-V Debug support
,
Alistair Francis
,
00:48
Re: [PATCH v2] disas/riscv.c: rvv: Add disas support for vector instructions
,
Alistair Francis
,
00:28
Re: [PATCH 1/4] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Alistair Francis
,
00:21
Re: [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Alistair Francis
,
00:00
September 22, 2022
Re: [PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Philippe Mathieu-Daudé
,
17:46
Re: [PATCH v2 2/3] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Philippe Mathieu-Daudé
,
17:43
Re: [PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Thomas Huth
,
12:17
[PATCH v2 3/3] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Tyler Ng
,
11:58
[PATCH v2 2/3] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Tyler Ng
,
11:58
[PATCH v2 1/3] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Tyler Ng
,
11:58
[PATCH v2 0/3] Implement the Opentitan watchdog
,
Tyler Ng
,
11:58
Re: [PATCH V4 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
Sunil V L
,
07:29
[PATCH 3/3] tests/qtest: sifive-e-aon-watchdog-test.c : Add QTest of watchdog of sifive_e
,
Tommy Wu
,
04:41
[PATCH 2/3] hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.
,
Tommy Wu
,
04:41
[PATCH 1/3] hw/misc: sifive_e_aon: Support the watchdog timer of HiFive 1 rev b.
,
Tommy Wu
,
04:41
[PATCH 0/3] Implement the watchdog timer of HiFive 1 rev b.
,
Tommy Wu
,
04:41
Re: [PATCH] include/hw/riscv/sifive_e.h: Fix the type of parent_obj of SiFiveEState.
,
Tommy Wu
,
04:12
Re: [PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Frank Chang
,
03:59
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
B
,
03:55
[PATCH] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Bernhard Beschow
,
03:53
September 21, 2022
Re: [PATCH 0/9] Deprecate sysbus_get_default() and get_system_memory() et. al
,
Peter Maydell
,
05:48
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Markus Armbruster
,
00:55
September 20, 2022
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Bernhard Beschow
,
19:24
Re: [PATCH 9/9] exec/address-spaces: Inline legacy functions
,
Bernhard Beschow
,
19:20
Re: [PATCH 8/9] softmmu/physmem: Let SysBusState absorb memory region and address space singletons
,
Bernhard Beschow
,
19:13
Re: [PATCH 2/9] exec/hwaddr.h: Add missing include
,
Bernhard Beschow
,
19:04
Re: [PATCH 0/9] Deprecate sysbus_get_default() and get_system_memory() et. al
,
Bernhard Beschow
,
19:00
Re: [PATCH 0/9] Deprecate sysbus_get_default() and get_system_memory() et. al
,
Bernhard Beschow
,
18:51
Re: [PATCH 0/9] Deprecate sysbus_get_default() and get_system_memory() et. al
,
Mark Cave-Ayland
,
11:38
Re: [PATCH 4/9] hw/ppc/spapr: Fix code style problems reported by checkpatch
,
Daniel Henrique Barboza
,
10:01
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Markus Armbruster
,
07:38
Re: [PATCH 0/9] Deprecate sysbus_get_default() and get_system_memory() et. al
,
Peter Maydell
,
05:56
Re: [PATCH 9/9] exec/address-spaces: Inline legacy functions
,
BALATON Zoltan
,
05:03
Re: [PATCH 8/9] softmmu/physmem: Let SysBusState absorb memory region and address space singletons
,
BALATON Zoltan
,
04:50
Re: [PATCH v14 0/5] Improve PMU support
,
Atish Kumar Patra
,
04:37
Re: [PATCH 5/9] exec/address-spaces: Wrap address space singletons into functions
,
Philippe Mathieu-Daudé
,
01:36
Re: [PATCH 9/9] exec/address-spaces: Inline legacy functions
,
Philippe Mathieu-Daudé
,
01:30
Re: [PATCH 9/9] exec/address-spaces: Inline legacy functions
,
Philippe Mathieu-Daudé
,
01:16
Re: [PATCH 8/9] softmmu/physmem: Let SysBusState absorb memory region and address space singletons
,
Philippe Mathieu-Daudé
,
01:12
Re: [PATCH 6/9] target/loongarch/cpu: Remove unneeded include directive
,
Philippe Mathieu-Daudé
,
00:57
Re: [PATCH 3/9] hw/core/sysbus: Resolve main_system_bus singleton
,
Philippe Mathieu-Daudé
,
00:53
Re: [PATCH 2/9] exec/hwaddr.h: Add missing include
,
Philippe Mathieu-Daudé
,
00:51
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Philippe Mathieu-Daudé
,
00:47
September 19, 2022
Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
,
Alistair Francis
,
19:53
Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
,
Alistair Francis
,
19:36
Re: [PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues
,
Alistair Francis
,
19:34
Re: [PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Alistair Francis
,
19:32
Re: [PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU
,
Alistair Francis
,
19:29
[PATCH 9/9] exec/address-spaces: Inline legacy functions
,
Bernhard Beschow
,
19:19
[PATCH 8/9] softmmu/physmem: Let SysBusState absorb memory region and address space singletons
,
Bernhard Beschow
,
19:19
[PATCH 6/9] target/loongarch/cpu: Remove unneeded include directive
,
Bernhard Beschow
,
19:19
[PATCH 7/9] hw/sysbus: Introduce dedicated struct SysBusState for TYPE_SYSTEM_BUS
,
Bernhard Beschow
,
19:19
[PATCH 5/9] exec/address-spaces: Wrap address space singletons into functions
,
Bernhard Beschow
,
19:19
[PATCH 4/9] hw/ppc/spapr: Fix code style problems reported by checkpatch
,
Bernhard Beschow
,
19:18
[PATCH 3/9] hw/core/sysbus: Resolve main_system_bus singleton
,
Bernhard Beschow
,
19:18
[PATCH 2/9] exec/hwaddr.h: Add missing include
,
Bernhard Beschow
,
19:18
[PATCH 1/9] hw/riscv/sifive_e: Fix inheritance of SiFiveEState
,
Bernhard Beschow
,
19:18
[PATCH 0/9] Deprecate sysbus_get_default() and get_system_memory() et. al
,
Bernhard Beschow
,
19:18
Re: [PATCH v2] disas/riscv.c: rvv: Add disas support for vector instructions
,
Alistair Francis
,
18:13
Re: [PATCH v14 0/5] Improve PMU support
,
Alistair Francis
,
18:08
Re: [PATCH] target/riscv: Check the correct exception cause in vector GDB stub
,
LIU Zhiwei
,
06:49
[PATCH v9 3/4] target/riscv: smstateen check for fcsr
,
Mayuresh Chitale
,
02:30
[PATCH v9 1/4] target/riscv: Add smstateen support
,
Mayuresh Chitale
,
02:29
[PATCH v9 2/4] target/riscv: smstateen check for h/s/envcfg
,
Mayuresh Chitale
,
02:29
[PATCH v9 4/4] target/riscv: smstateen knobs
,
Mayuresh Chitale
,
02:29
[PATCH v9 0/4] RISC-V Smstateen support
,
Mayuresh Chitale
,
02:29
September 18, 2022
[PATCH] target/riscv: Check the correct exception cause in vector GDB stub
,
frank . chang
,
04:29
September 17, 2022
Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
,
Philippe Mathieu-Daudé
,
17:03
Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
,
Philippe Mathieu-Daudé
,
17:01
September 16, 2022
Re: [PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
,
Wilfred Mallawa
,
20:57
Re: [PATCH 2/3] hw/riscv: opentitan: Fixup resetvec
,
Wilfred Mallawa
,
20:53
Re: [PATCH 1/3] target/riscv: Set the CPU resetvec directly
,
Wilfred Mallawa
,
20:53
Re: [PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions
,
LIU Zhiwei
,
05:13
Re: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions
,
Richard Henderson
,
03:59
Re: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions
,
LIU Zhiwei
,
02:44
Re: [PATCH 01/11] riscv: Add privilege level to DisasContext
,
LIU Zhiwei
,
02:22
Re: [PATCH 01/11] riscv: Add privilege level to DisasContext
,
Richard Henderson
,
02:05
Re: [PATCH 01/11] riscv: Add privilege level to DisasContext
,
Richard Henderson
,
02:00
September 15, 2022
Re: [PATCH 01/11] riscv: Add privilege level to DisasContext
,
LIU Zhiwei
,
22:52
Re: [PATCH 02/11] RISC-V: Adding T-Head CMO instructions
,
LIU Zhiwei
,
22:48
Re: [PATCH v2 1/8] target/riscv: debug: Determine the trigger type from tdata1.type
,
LIU Zhiwei
,
22:43
Re: [PATCH v2 6/8] target/riscv: debug: Create common trigger actions function
,
LIU Zhiwei
,
22:41
Re: [PATCH v2 5/8] target/riscv: debug: Introduce tinfo CSR
,
LIU Zhiwei
,
22:27
Re: [PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value can be written
,
LIU Zhiwei
,
22:00
Re: [PATCH v2 3/8] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
,
LIU Zhiwei
,
21:59
Re: [PATCH v2 2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
,
LIU Zhiwei
,
21:55
Re: [PATCH v2 1/8] target/riscv: debug: Determine the trigger type from tdata1.type
,
LIU Zhiwei
,
21:54
Re: [PATCH v4 0/4] Fix dt-validate issues on qemu dtbdumps due to dt-bindings
,
Conor.Dooley
,
14:46
Re: [PATCH V4 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
gaosong
,
09:22
Re: [PATCH V4 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
Sunil V L
,
07:59
September 14, 2022
[PATCH 3/3] hw/riscv: opentitan: Expose the resetvec as a SoC property
,
Alistair Francis
,
06:11
[PATCH 1/3] target/riscv: Set the CPU resetvec directly
,
Alistair Francis
,
06:11
[PATCH 2/3] hw/riscv: opentitan: Fixup resetvec
,
Alistair Francis
,
06:11
[PATCH 0/3] hw/riscv: opentitan: Fixup resetvec issues
,
Alistair Francis
,
06:11
September 09, 2022
Re: [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension
,
Christoph Müllner
,
13:21
Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions
,
Christoph Müllner
,
13:21
[PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU
,
leon
,
11:23
[PATCH v2 8/8] target/riscv: debug: Add initial support of type 6 trigger
,
Bin Meng
,
09:42
[PATCH v2 7/8] target/riscv: debug: Check VU/VS modes for type 2 trigger
,
Bin Meng
,
09:42
[PATCH v2 6/8] target/riscv: debug: Create common trigger actions function
,
Bin Meng
,
09:42
[PATCH v2 5/8] target/riscv: debug: Introduce tinfo CSR
,
Bin Meng
,
09:42
[PATCH v2 4/8] target/riscv: debug: Restrict the range of tselect value can be written
,
Bin Meng
,
09:42
[PATCH v2 3/8] target/riscv: debug: Introduce tdata1, tdata2, and tdata3 CSRs
,
Bin Meng
,
09:42
[PATCH v2 2/8] target/riscv: debug: Introduce build_tdata1() to build tdata1 register content
,
Bin Meng
,
09:42
[PATCH v2 1/8] target/riscv: debug: Determine the trigger type from tdata1.type
,
Bin Meng
,
09:42
[PATCH v2 0/8] target/riscv: Improve RISC-V Debug support
,
Bin Meng
,
09:42
September 08, 2022
Re: [PATCH 3/4] hw/timer: ibex_timer.c: Update register addresses
,
Tyler Ng
,
18:04
Re: [PATCH 1/4] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Tyler Ng
,
18:04
Re: [PATCH v3] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
,
Alistair Francis
,
08:32
Re: [PATCH] target/riscv: Remove sideleg and sedeleg
,
Alistair Francis
,
08:32
Re: [PATCH 4/4] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Alistair Francis
,
08:20
Re: [PATCH 3/4] hw/timer: ibex_timer.c: Update register addresses
,
Alistair Francis
,
07:56
Re: [PATCH 1/4] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Alistair Francis
,
07:52
Re: [PATCH v4 2/4] hw/ssi: ibex_spi: fixup coverity issue
,
Alistair Francis
,
07:30
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflashy
,
Gerd Hoffmann
,
07:20
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
06:44
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflashy
,
Sunil V L
,
06:26
Re: [PATCH 2/2] target/riscv: fence: reconcile with specification
,
Philipp Tomsich
,
05:28
Re: [PATCH v3] target/riscv: fix csr check for cycle{h}, instret{h}, time{h}, hpmcounter3-31{h}
,
Alistair Francis
,
05:28
Re: [PATCH 2/2] target/riscv: fence: reconcile with specification
,
Alistair Francis
,
05:25
Re: [PATCH] target/riscv: Remove sideleg and sedeleg
,
Alistair Francis
,
05:22
Re: [PATCH V4 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
,
Alistair Francis
,
05:21
Re: [RFC PATCH] docs/system: clean up code escape for riscv virt platform
,
Alistair Francis
,
05:20
Re: [PATCH V4 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
Alistair Francis
,
05:18
Re: [PATCH v4 0/4] hw/ssi: ibex_spi: cleanup and fixup bugs
,
Alistair Francis
,
05:09
Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs
,
Christoph Müllner
,
05:02
Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs
,
Richard Henderson
,
04:56
Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs
,
Christoph Müllner
,
04:23
Re: [PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs
,
Richard Henderson
,
03:46
Re: [PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension
,
Richard Henderson
,
03:45
Re: [PATCH 03/11] RISC-V: Adding T-Head SYNC instructions
,
Richard Henderson
,
03:30
September 07, 2022
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Gerd Hoffmann
,
03:10
September 06, 2022
Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Tyler Ng
,
11:13
Re: [PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU
,
Leon Schuermann
,
10:46
Re: [PATCH V4 1/3] hw/arm,loongarch: Move load_image_to_fw_cfg() to common location
,
Philippe Mathieu-Daudé
,
09:32
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
08:32
Re: [RFC PATCH] docs/system: clean up code escape for riscv virt platform
,
Alex Bennée
,
08:27
[PATCH 07/11] RISC-V: Adding T-Head XMAE support
,
Christoph Muellner
,
08:23
[PATCH 06/11] RISC-V: Adding T-Head multiply-accumulate instructions
,
Christoph Muellner
,
08:23
[PATCH 10/11] RISC-V: Adding T-Head FMemIdx extension
,
Christoph Muellner
,
08:23
[PATCH 11/11] RISC-V: Add initial support for T-Head C906 and C910 CPUs
,
Christoph Muellner
,
08:23
[PATCH 09/11] RISC-V: Adding T-Head MemIdx extension
,
Christoph Muellner
,
08:23
[PATCH 08/11] RISC-V: Adding T-Head MemPair extension
,
Christoph Muellner
,
08:23
[PATCH 02/11] RISC-V: Adding T-Head CMO instructions
,
Christoph Muellner
,
08:23
[PATCH 04/11] RISC-V: Adding T-Head Bitmanip instructions
,
Christoph Muellner
,
08:23
[PATCH 05/11] RISC-V: Adding T-Head CondMov instructions
,
Christoph Muellner
,
08:23
[PATCH 03/11] RISC-V: Adding T-Head SYNC instructions
,
Christoph Muellner
,
08:23
[PATCH 01/11] riscv: Add privilege level to DisasContext
,
Christoph Muellner
,
08:23
[PATCH 00/11] Add support for the T-Head vendor extensions
,
Christoph Muellner
,
08:22
Re: [RFC PATCH] docs/system: clean up code escape for riscv virt platform
,
Alistair Francis
,
07:38
Re: [PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Gerd Hoffmann
,
06:41
[PATCH V4 3/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
05:02
[PATCH V4 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
05:02
[PATCH V4 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
,
Sunil V L
,
05:02
[PATCH V4 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
Sunil V L
,
05:02
Re: [PATCH v2 0/7] Allow semihosting from user mode
,
Richard Henderson
,
03:51
Re: [PATCH V3 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
,
Andrew Jones
,
03:20
Re: [PATCH V3 1/3] hw/arm,loongarch: Move load_image_to_fw_cfg() to common location
,
Andrew Jones
,
03:20
Re: [PATCH V3 3/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Andrew Jones
,
03:20
[PATCH V3 3/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
00:25
[PATCH V3 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
,
Sunil V L
,
00:25
[PATCH V3 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
Sunil V L
,
00:25
[PATCH V3 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
00:25
Re: [PATCH V2 1/3] hw/arm,loongarch: Move load_image_to_fw_cfg() to common location
,
Sunil V L
,
00:21
September 05, 2022
Re: [PATCH V2 1/3] hw/arm,loongarch: Move load_image_to_fw_cfg() to common location
,
Peter Maydell
,
17:20
[PATCH V2 3/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
14:23
[PATCH V2 2/3] hw/riscv: virt: Move create_fw_cfg() prior to loading kernel
,
Sunil V L
,
14:23
[PATCH V2 1/3] hw/arm, loongarch: Move load_image_to_fw_cfg() to common location
,
Sunil V L
,
14:23
[PATCH V2 0/3] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
14:23
[RFC PATCH] docs/system: clean up code escape for riscv virt platform
,
Alex Bennée
,
12:39
Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Philippe Mathieu-Daudé
,
11:09
Re: [PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Andrew Jones
,
09:15
Re: [PATCH] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
07:16
Re: [PATCH] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Andrew Jones
,
04:07
[PATCH] hw/riscv: virt: Enable booting S-mode firmware from pflash
,
Sunil V L
,
00:29
September 04, 2022
[PATCH] target/riscv/pmp: fix non-translated page size address checks w/ MPU
,
leon
,
15:30
September 02, 2022
Re: [PATCH] target/riscv: Implement PMU CSR predicate function for U-mode
,
Aurelien Jarno
,
13:28
[PATCH] target/riscv: Implement PMU CSR predicate function for U-mode
,
Aurelien Jarno
,
12:47
September 01, 2022
[PATCH 3/4] hw/timer: ibex_timer.c: Update register addresses
,
Tyler Ng
,
21:22
[PATCH 1/4] hw/watchdog: wdt_ibex_aon.c: Implement the watchdog for the OpenTitan
,
Tyler Ng
,
21:22
[PATCH 4/4] hw/timer: ibex_timer.c: Add support for writes to mtime
,
Tyler Ng
,
21:22
[PATCH 0/4] Implement the OpenTitan watchdog
,
Tyler Ng
,
21:22
[PATCH 2/4] hw/intc: sifive_plic.c: Fix interrupt priority index.
,
Tyler Ng
,
21:22
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