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[PATCH v9 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v9 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs |
Date: |
Thu, 19 Jan 2023 18:37:04 -0300 |
Hi,
In this version I changed the patch order to avoid having a patch that
would trigger the 32 bit regression Alistair observed. Patch 3 is now
the first patch.
I've also addressed the comments from Bin and Phil.
Patches based on riscv-to-apply.next.
Changes from v8:
- patch 1 (former 3):
- comment changes
- now open code '32' instead of using a macro
- v8 link: https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg03254.html
Daniel Henrique Barboza (3):
hw/riscv: clear kernel_entry higher bits from load_elf_ram_sym()
hw/riscv/boot.c: consolidate all kernel init in riscv_load_kernel()
hw/riscv/boot.c: make riscv_load_initrd() static
hw/riscv/boot.c | 96 ++++++++++++++++++++++++++------------
hw/riscv/microchip_pfsoc.c | 12 +----
hw/riscv/opentitan.c | 4 +-
hw/riscv/sifive_e.c | 4 +-
hw/riscv/sifive_u.c | 12 +----
hw/riscv/spike.c | 14 ++----
hw/riscv/virt.c | 12 +----
include/hw/riscv/boot.h | 3 +-
8 files changed, 82 insertions(+), 75 deletions(-)
--
2.39.0
- [PATCH v9 0/3] hw/riscv: clear kernel_entry high bits with 32bit CPUs,
Daniel Henrique Barboza <=