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From: | Palmer Dabbelt |
Subject: | Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled |
Date: | Wed, 01 Mar 2023 16:58:01 -0800 (PST) |
On Wed, 01 Mar 2023 16:30:52 PST (-0800), Bin Meng wrote:
On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt <palmer@dabbelt.com> wrote:On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote: > On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote: >> >> >> On 2023/2/28 18:40, Bin Meng wrote: >> > There is no need to generate the CSR XML if the Zicsr extension >> > is not enabled. >> >> Should we generate the FPU XML or Vector XML when Zicsr is not enabled? > > Good point. I think we should disable that too. Seems reasonable. Did you want to do that as part of a v3, or just as a follow-on fix?I looked at this further. The FPU / Vector XML is guarded by the " env->misa_ext" check. If Zicsr is disabled while F or V extension is off, QEMU will error out in riscv_cpu_realize() earlier before the gdbstub init. So current patch should be fine.
There's a merge conflict that git auto-resolved as diff --cc target/riscv/csr.c index a1ecf62305,3a7e0217e2..a2cf3536f0 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c@@@ -90,10 -53,10 +53,9 @@@ static RISCVException fs(CPURISCVState static RISCVException vs(CPURISCVState *env, int csrno)
{ - CPUState *cs = env_cpu(env); - RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPU *cpu = env_archcpu(env);- if (env->misa_ext & RVV ||
- cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) { + if (cpu->cfg.ext_zve32f) { #if !defined(CONFIG_USER_ONLY) if (!env->debugger && !riscv_cpu_vector_enabled(env)) { return RISCV_EXCP_ILLEGAL_INST; which looks correct to me. It's passing my tests and queued up, but LMK if something looks wrong. Thanks!
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