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[PULL 40/59] target/riscv: Allow debugger to access sstc CSRs
From: |
Palmer Dabbelt |
Subject: |
[PULL 40/59] target/riscv: Allow debugger to access sstc CSRs |
Date: |
Fri, 3 Mar 2023 00:37:21 -0800 |
From: Bin Meng <bmeng@tinylab.org>
At present with a debugger attached sstc CSRs can only be accssed
when CPU is in M-mode, or configured correctly.
Fix it by adjusting their predicate() routine logic so that the
static config check comes before the run-time check, as well as
adding a debugger check.
Signed-off-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Message-ID: <20230228104035.1879882-17-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
target/riscv/csr.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a0e70f5ba0..020c3f524f 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -952,6 +952,19 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+ if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
+ hmode_check = true;
+ }
+
+ RISCVException ret = hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ if (ret != RISCV_EXCP_NONE) {
+ return ret;
+ }
+
+ if (env->debugger) {
+ return RISCV_EXCP_NONE;
+ }
+
if (env->priv == PRV_M) {
return RISCV_EXCP_NONE;
}
@@ -972,11 +985,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
- if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
- hmode_check = true;
- }
-
- return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+ return RISCV_EXCP_NONE;
}
static RISCVException sstc_32(CPURISCVState *env, int csrno)
--
2.39.2
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, (continued)
- [PULL 34/59] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64, Palmer Dabbelt, 2023/03/03
- [PULL 30/59] target/riscv: Coding style fixes in csr.c, Palmer Dabbelt, 2023/03/03
- [PULL 35/59] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 36/59] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml, Palmer Dabbelt, 2023/03/03
- [PULL 39/59] target/riscv: Allow debugger to access {h, s}stateen CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 43/59] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages, Palmer Dabbelt, 2023/03/03
- [PULL 44/59] RISC-V: XTheadMemPair: Remove register restrictions for store-pair, Palmer Dabbelt, 2023/03/03
- [PULL 38/59] target/riscv: Allow debugger to access seed CSR, Palmer Dabbelt, 2023/03/03
- [PULL 37/59] target/riscv: Allow debugger to access user timer and counter CSRs, Palmer Dabbelt, 2023/03/03
- [PULL 46/59] hw/riscv: Skip re-generating DT nodes for a given DTB, Palmer Dabbelt, 2023/03/03
- [PULL 40/59] target/riscv: Allow debugger to access sstc CSRs,
Palmer Dabbelt <=
- [PULL 41/59] target/riscv: Drop priv level check in mseccfg predicate(), Palmer Dabbelt, 2023/03/03
- [PULL 42/59] target/riscv: Group all predicate() routines together, Palmer Dabbelt, 2023/03/03
- [PULL 48/59] target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions, Palmer Dabbelt, 2023/03/03
- [PULL 45/59] target/riscv: Add support for Zicond extension, Palmer Dabbelt, 2023/03/03
- [PULL 55/59] target/riscv/csr.c: simplify mctr(), Palmer Dabbelt, 2023/03/03
- [PULL 47/59] hw/riscv: Move the dtb load bits outside of create_fdt(), Palmer Dabbelt, 2023/03/03
- [PULL 49/59] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg, Palmer Dabbelt, 2023/03/03
- [PULL 50/59] target/riscv: Add csr support for svadu, Palmer Dabbelt, 2023/03/03
- [PULL 51/59] target/riscv: Add *envcfg.PBMTE related check in address translation, Palmer Dabbelt, 2023/03/03
- [PULL 52/59] target/riscv: Add *envcfg.HADE related check in address translation, Palmer Dabbelt, 2023/03/03