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[PATCH v12 01/10] target/riscv: add cfg properties for Zc* extension
From: |
Weiwei Li |
Subject: |
[PATCH v12 01/10] target/riscv: add cfg properties for Zc* extension |
Date: |
Tue, 7 Mar 2023 16:13:54 +0800 |
Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension.
Add check for these properties.
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 43 +++++++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h | 6 ++++++
2 files changed, 49 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 1e97473af2..df7eed57af 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -939,6 +939,49 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU
*cpu, Error **errp)
}
}
+ if (cpu->cfg.ext_c) {
+ cpu->cfg.ext_zca = true;
+ if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) {
+ cpu->cfg.ext_zcf = true;
+ }
+ if (cpu->cfg.ext_d) {
+ cpu->cfg.ext_zcd = true;
+ }
+ }
+
+ if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
+ error_setg(errp, "Zcf extension is only relevant to RV32");
+ return;
+ }
+
+ if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) {
+ error_setg(errp, "Zcf extension requires F extension");
+ return;
+ }
+
+ if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) {
+ error_setg(errp, "Zcd extension requires D extension");
+ return;
+ }
+
+ if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
+ cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
+ error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
+ "extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
+ error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
+ "Zcd extension");
+ return;
+ }
+
+ if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
+ error_setg(errp, "Zcmt extension requires Zicsr extension");
+ return;
+ }
+
if (cpu->cfg.ext_zk) {
cpu->cfg.ext_zkn = true;
cpu->cfg.ext_zkr = true;
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..a2426ec479 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -438,6 +438,12 @@ struct RISCVCPUConfig {
bool ext_zbkc;
bool ext_zbkx;
bool ext_zbs;
+ bool ext_zca;
+ bool ext_zcb;
+ bool ext_zcd;
+ bool ext_zcf;
+ bool ext_zcmp;
+ bool ext_zcmt;
bool ext_zk;
bool ext_zkn;
bool ext_zknd;
--
2.25.1
- [PATCH v12 00/10] support subsets of code size reduction extension, Weiwei Li, 2023/03/07
- [PATCH v12 05/10] target/riscv: add support for Zcb extension, Weiwei Li, 2023/03/07
- [PATCH v12 03/10] target/riscv: add support for Zcf extension, Weiwei Li, 2023/03/07
- [PATCH v12 01/10] target/riscv: add cfg properties for Zc* extension,
Weiwei Li <=
- [PATCH v12 08/10] target/riscv: expose properties for Zc* extension, Weiwei Li, 2023/03/07
- [PATCH v12 04/10] target/riscv: add support for Zcd extension, Weiwei Li, 2023/03/07
- [PATCH v12 06/10] target/riscv: add support for Zcmp extension, Weiwei Li, 2023/03/07
- [PATCH v12 02/10] target/riscv: add support for Zca extension, Weiwei Li, 2023/03/07
- [PATCH v12 07/10] target/riscv: add support for Zcmt extension, Weiwei Li, 2023/03/07
- [PATCH v12 10/10] target/riscv: Add support for Zce, Weiwei Li, 2023/03/07
- [PATCH v12 09/10] disas/riscv.c: add disasm support for Zc*, Weiwei Li, 2023/03/07
- Re: [PATCH v12 00/10] support subsets of code size reduction extension, liweiwei, 2023/03/24