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[PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro |
Date: |
Wed, 8 Mar 2023 17:19:12 -0300 |
PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is
used in all generic CPUs:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
When a new PRIV version is made available we can just update the LATEST
macro.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
---
target/riscv/cpu.c | 8 ++++----
target/riscv/cpu.h | 1 +
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 964817b9d2..62ef11180f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -338,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj)
VM_1_10_SV32 : VM_1_10_SV57);
#endif
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
register_cpu_props(obj);
}
@@ -350,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj)
set_misa(env, MXL_RV64, 0);
register_cpu_props(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -426,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj)
set_misa(env, MXL_RV128, 0);
register_cpu_props(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
#endif
@@ -439,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj)
set_misa(env, MXL_RV32, 0);
register_cpu_props(obj);
/* Set latest version of privileged specification */
- env->priv_ver = PRIV_VERSION_1_12_0;
+ env->priv_ver = PRIV_VERSION_LATEST;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 638e47c75a..af2e4b7695 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -89,6 +89,7 @@ enum {
PRIV_VERSION_1_11_0,
PRIV_VERSION_1_12_0,
};
+#define PRIV_VERSION_LATEST PRIV_VERSION_1_12_0
#define VEXT_VERSION_1_00_0 0x00010000
--
2.39.2
- [PATCH for-8.1 00/17] centralize CPU extensions logic, Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 04/17] target/riscv: add PRIV_VERSION_LATEST macro,
Daniel Henrique Barboza <=
- [PATCH for-8.1 05/17] target/riscv/cpu.c: add riscv_cpu_validate_priv_spec(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 06/17] target/riscv: move realize() validations to riscv_cpu_validate_set_extensions(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 07/17] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 08/17] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 09/17] target/riscv/cpu.c: set cpu config in set_misa(), Daniel Henrique Barboza, 2023/03/08
- [PATCH for-8.1 10/17] target/riscv/cpu.c: redesign register_cpu_props(), Daniel Henrique Barboza, 2023/03/08