[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v4 03/19] target/riscv/cpu.c: restrict 'mvendorid' value
From: |
Daniel Henrique Barboza |
Subject: |
[PATCH v4 03/19] target/riscv/cpu.c: restrict 'mvendorid' value |
Date: |
Mon, 26 Jun 2023 19:01:53 -0300 |
We're going to change the handling of mvendorid/marchid/mimpid by the
KVM driver. Since these are always present in all CPUs let's put the
same validation for everyone.
It doesn't make sense to allow 'mvendorid' to be different than it
is already set in named (vendor) CPUs. Generic (dynamic) CPUs can have
any 'mvendorid' they want.
Change 'mvendorid' to be a class property created via
'object_class_property_add', instead of using the DEFINE_PROP_UINT32()
macro. This allow us to define a custom setter for it that will verify,
for named CPUs, if mvendorid is different than it is already set by the
CPU. This is the error thrown for the 'veyron-v1' CPU if 'mvendorid' is
set to an invalid value:
$ qemu-system-riscv64 -M virt -nographic -cpu veyron-v1,mvendorid=2
qemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.mvendorid=2:
Unable to change veyron-v1-riscv-cpu mvendorid (0x61f)
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 38 +++++++++++++++++++++++++++++++++++++-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e515dde208..b65958a887 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1738,7 +1738,6 @@ static void riscv_cpu_add_user_properties(Object *obj)
static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
- DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
@@ -1825,6 +1824,40 @@ static const struct TCGCPUOps riscv_tcg_ops = {
#endif /* !CONFIG_USER_ONLY */
};
+static bool riscv_cpu_is_dynamic(Object *cpu_obj)
+{
+ return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
+}
+
+static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
+ RISCVCPU *cpu = RISCV_CPU(obj);
+ uint32_t prev_val = cpu->cfg.mvendorid;
+ uint32_t value;
+
+ if (!visit_type_uint32(v, name, &value, errp)) {
+ return;
+ }
+
+ if (!dynamic_cpu && prev_val != value) {
+ error_setg(errp, "Unable to change %s mvendorid (0x%x)",
+ object_get_typename(obj), prev_val);
+ return;
+ }
+
+ cpu->cfg.mvendorid = value;
+}
+
+static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ bool value = RISCV_CPU(obj)->cfg.mvendorid;
+
+ visit_type_bool(v, name, &value, errp);
+}
+
static void riscv_cpu_class_init(ObjectClass *c, void *data)
{
RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
@@ -1856,6 +1889,9 @@ static void riscv_cpu_class_init(ObjectClass *c, void
*data)
cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
cc->tcg_ops = &riscv_tcg_ops;
+ object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid,
+ cpu_set_mvendorid, NULL, NULL);
+
device_class_set_props(dc, riscv_cpu_properties);
}
--
2.41.0
- [PATCH v4 00/19] target/riscv, KVM: fixes and enhancements, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 01/19] target/riscv: skip features setup for KVM CPUs, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 02/19] hw/riscv/virt.c: skip 'mmu-type' FDT if satp mode not set, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 06/19] target/riscv: use KVM scratch CPUs to init KVM properties, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 04/19] target/riscv/cpu.c: restrict 'mimpid' value, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 03/19] target/riscv/cpu.c: restrict 'mvendorid' value,
Daniel Henrique Barboza <=
- [PATCH v4 05/19] target/riscv/cpu.c: restrict 'marchid' value, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 07/19] target/riscv: read marchid/mimpid in kvm_riscv_init_machine_ids(), Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 08/19] target/riscv: handle mvendorid/marchid/mimpid for KVM CPUs, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 10/19] target/riscv/kvm.c: init 'misa_ext_mask' with scratch CPU, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 12/19] target/riscv: add KVM specific MISA properties, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 11/19] target/riscv/cpu: add misa_ext_info_arr[], Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 09/19] linux-headers: Update to v6.4-rc1, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 13/19] target/riscv/kvm.c: update KVM MISA bits, Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 15/19] target/riscv/cpu.c: remove priv_ver check from riscv_isa_string_ext(), Daniel Henrique Barboza, 2023/06/26
- [PATCH v4 17/19] target/riscv: update multi-letter extension KVM properties, Daniel Henrique Barboza, 2023/06/26