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[RFC PATCH v2 2/2] hw/riscv: hart: allow other cpu instance
From: |
Nikita Shubin |
Subject: |
[RFC PATCH v2 2/2] hw/riscv: hart: allow other cpu instance |
Date: |
Thu, 14 Sep 2023 11:07:40 +0300 |
From: Nikita Shubin <n.shubin@yadro.com>
Allow using instances derivative from RISCVCPU
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
---
hw/riscv/riscv_hart.c | 20 ++++++++++++--------
include/hw/riscv/riscv_hart.h | 2 +-
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 613ea2aaa0..020ba18e8b 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -43,24 +43,28 @@ static void riscv_harts_cpu_reset(void *opaque)
}
static bool riscv_hart_realize(RISCVHartArrayState *s, int idx,
- char *cpu_type, Error **errp)
+ char *cpu_type, size_t size, Error **errp)
{
- object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_type);
- qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec);
- s->harts[idx].env.mhartid = s->hartid_base + idx;
- qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]);
- return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp);
+ RISCVCPU *hart = s->harts[idx];
+ object_initialize_child_internal(OBJECT(s), "harts[*]",
+ hart, size, cpu_type);
+ qdev_prop_set_uint64(DEVICE(hart), "resetvec", s->resetvec);
+ hart->env.mhartid = s->hartid_base + idx;
+ qemu_register_reset(riscv_harts_cpu_reset, hart);
+ return qdev_realize(DEVICE(hart), NULL, errp);
}
static void riscv_harts_realize(DeviceState *dev, Error **errp)
{
RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
+ size_t size = object_type_get_instance_size(s->cpu_type);
int n;
- s->harts = g_new0(RISCVCPU, s->num_harts);
+ s->harts = g_new0(RISCVCPU *, s->num_harts);
for (n = 0; n < s->num_harts; n++) {
- if (!riscv_hart_realize(s, n, s->cpu_type, errp)) {
+ s->harts[n] = RISCV_CPU(object_new(s->cpu_type));
+ if (!riscv_hart_realize(s, n, s->cpu_type, size, errp)) {
return;
}
}
diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 912b4a2682..5f6ef06411 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -38,7 +38,7 @@ struct RISCVHartArrayState {
uint32_t hartid_base;
char *cpu_type;
uint64_t resetvec;
- RISCVCPU *harts;
+ RISCVCPU **harts;
};
#endif
--
2.39.2