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[PATCH v4 1/6] target/riscv: Without H-mode mask all HS mode inturrupts
From: |
Rajnesh Kanwal |
Subject: |
[PATCH v4 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie. |
Date: |
Thu, 12 Oct 2023 11:00:58 +0100 |
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 4b4ab56c40..d99d954ff3 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1525,7 +1525,7 @@ static RISCVException rmw_mie64(CPURISCVState *env, int
csrno,
env->mie = (env->mie & ~mask) | (new_val & mask);
if (!riscv_has_ext(env, RVH)) {
- env->mie &= ~((uint64_t)MIP_SGEIP);
+ env->mie &= ~((uint64_t)HS_MODE_INTERRUPTS);
}
return RISCV_EXCP_NONE;
--
2.34.1
- [PATCH v4 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support, Rajnesh Kanwal, 2023/10/12
- [PATCH v4 1/6] target/riscv: Without H-mode mask all HS mode inturrupts in mie.,
Rajnesh Kanwal <=
- [PATCH v4 3/6] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Rajnesh Kanwal, 2023/10/12
- [PATCH v4 2/6] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 6/6] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 4/6] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Rajnesh Kanwal, 2023/10/12
- [PATCH v4 5/6] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Rajnesh Kanwal, 2023/10/12