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Re: [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuou
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous |
Date: |
Mon, 16 Oct 2023 14:23:08 +1000 |
On Fri, Oct 13, 2023 at 9:03 PM Rob Bradford <rbradford@rivosinc.com> wrote:
>
> Check the PMU available bitmask when checking if a counter is valid
> rather than comparing the index against the number of PMUs.
>
> Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/csr.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 85a31dc420..4383805fa3 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -182,7 +182,8 @@ static RISCVException zcmt(CPURISCVState *env, int csrno)
> #if !defined(CONFIG_USER_ONLY)
> static RISCVException mctr(CPURISCVState *env, int csrno)
> {
> - int pmu_num = riscv_cpu_cfg(env)->pmu_num;
> + RISCVCPU *cpu = env_archcpu(env);
> + uint32_t pmu_avail_ctrs = cpu->pmu_avail_ctrs;
> int ctr_index;
> int base_csrno = CSR_MHPMCOUNTER3;
>
> @@ -191,7 +192,7 @@ static RISCVException mctr(CPURISCVState *env, int csrno)
> base_csrno += 0x80;
> }
> ctr_index = csrno - base_csrno;
> - if (!pmu_num || ctr_index >= pmu_num) {
> + if ((BIT(ctr_index) & pmu_avail_ctrs >> 3) == 0) {
> /* The PMU is not enabled or counter is out of range */
> return RISCV_EXCP_ILLEGAL_INST;
> }
> --
> 2.41.0
>
>
- [PATCH v3 0/6] Support discontinuous PMU counters, Rob Bradford, 2023/10/13
- [PATCH v3 1/6] target/riscv: Propagate error from PMU setup, Rob Bradford, 2023/10/13
- [PATCH v3 5/6] docs/about/deprecated: Document RISC-V "pmu-num" deprecation, Rob Bradford, 2023/10/13
- [PATCH v3 4/6] target/riscv: Add "pmu-mask" property to replace "pmu-num", Rob Bradford, 2023/10/13
- [PATCH v3 6/6] target/riscv: Use MAKE_64BIT_MASK instead of custom macro, Rob Bradford, 2023/10/13
- [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous, Rob Bradford, 2023/10/13
- Re: [PATCH v3 2/6] target/riscv: Don't assume PMU counters are continuous,
Alistair Francis <=
- [PATCH v3 3/6] target/riscv: Use existing PMU counter mask in FDT generation, Rob Bradford, 2023/10/13