Re: [PATCH 3/3] target/riscv: Ensure mideleg is set correctly on reset

[Daniel Henrique Barboza]

On 1/7/24 21:13, Alistair Francis wrote:
> Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor is
> enabled. We currently only set them on accesses to mideleg, but they
> aren't correctly set on reset. Let's ensure they are always the correct
> value.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1617
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/cpu.c | 8 ++++++++
>   1 file changed, 8 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index b07a76ef6b..e20ff46c23 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -891,6 +891,14 @@ static void riscv_cpu_reset_hold(Object *obj)
>       /* mmte is supposed to have pm.current hardwired to 1 */
>       env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
>   
> +    /*
> +     * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor
> +     * extension is enabled.
> +     */
> +    if (riscv_has_ext(env, RVH)) {
> +        env->mideleg |= HS_MODE_INTERRUPTS;
> +    }
> +
>       /*
>        * Clear mseccfg and unlock all the PMP entries upon reset.
>        * This is allowed as per the priv and smepmp specifications