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Re: [PATCH 0/3] target/riscv: A few bug fixes and Coverity fix
From: |
Alistair Francis |
Subject: |
Re: [PATCH 0/3] target/riscv: A few bug fixes and Coverity fix |
Date: |
Tue, 9 Jan 2024 10:38:50 +1000 |
On Mon, Jan 8, 2024 at 10:13 AM Alistair Francis <alistair23@gmail.com> wrote:
>
> A few bug fixes for some Gitlab issues and a Coverity fix
>
> Alistair Francis (3):
> target/riscv: Assert that the CSR numbers will be correct
> target/riscv: Don't adjust vscause for exceptions
> target/riscv: Ensure mideleg is set correctly on reset
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.c | 8 ++++++++
> target/riscv/cpu_helper.c | 4 ++--
> target/riscv/csr.c | 5 ++++-
> 3 files changed, 14 insertions(+), 3 deletions(-)
>
> --
> 2.43.0
>