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Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA ex
From: |
Rob Bradford |
Subject: |
Re: Re: Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension |
Date: |
Fri, 12 Jan 2024 16:54:08 +0000 |
User-agent: |
Evolution 3.48.4 (3.48.4-1.module_f38+17164+63eeee4a) |
On Fri, 2024-01-12 at 17:08 +0100, Andrew Jones wrote:
> On Thu, Jan 11, 2024 at 03:17:25PM +0000, Rob Bradford wrote:
> > + Ved
> >
> > On Thu, 2024-01-11 at 14:14 +0100, Andrew Jones wrote:
> > > On Thu, Jan 11, 2024 at 02:07:34PM +0100, Andrew Jones wrote:
> > > > On Tue, Jan 09, 2024 at 05:07:35PM +0000, Rob Bradford wrote:
> > > > > Add the infrastructure for the 'B' extension which is the
> > > > > union
> > > > > of the
> > > > > Zba, Zbb and Zbs instructions.
> > > > >
> > > > > Signed-off-by: Rob Bradford <rbradford@rivosinc.com>
> > > > > ---
> > > > > target/riscv/cpu.c | 5 +++--
> > > > > target/riscv/cpu.h | 1 +
> > > > > target/riscv/tcg/tcg-cpu.c | 1 +
> > > > > 3 files changed, 5 insertions(+), 2 deletions(-)
> > > > >
> > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > > > > index b07a76ef6b..22f8e527ff 100644
> > > > > --- a/target/riscv/cpu.c
> > > > > +++ b/target/riscv/cpu.c
> > > > > @@ -38,9 +38,9 @@
> > > > > #include "tcg/tcg.h"
> > > > >
> > > > > /* RISC-V CPU definitions */
> > > > > -static const char riscv_single_letter_exts[] =
> > > > > "IEMAFDQCPVH";
> > > > > +static const char riscv_single_letter_exts[] =
> > > > > "IEMAFDQCBPVH";
> > > >
> > > > Is there a corresponding proposed change to table 29.1 of the
> > > > nonpriv spec
> > > > which states B comes after C and before P? If so, can you
> > > > provide a
> > > > link
> > > > to it? Otherwise, how do we know that?
> > >
> > > Oh, I see. The unpriv spec B chapter comes after the C chapter
> > > (and
> > > before
> > > J, P, ...). I still wonder if we'll have a 29.1 table update with
> > > the
> > > ratification of this extension though.
> > >
> > >
> >
> > I agree it's a bit confusing - but the order is established by the
> > table in the unprivileged spec and the table explanation also makes
> > this clear.
> >
> > """
> > Table 27.1: Standard ISA extension names. The table also defines
> > the
> > canonical order in which
> > extension names must appear in the name string, with top-to-bottom
> > in
> > table indicating first-to-last
> > in the name string, e.g., RV32IMACV is legal, whereas RV32IMAVC is
> > not.
> > """
>
> Yes, this is the table I was referring to when I referenced "table
> 29.1 of
> the nonpriv spec". Since there's a chance I was looking at too old a
> spec
> I've now gone straight to the source,
>
> https://github.com/riscv/riscv-isa-manual/blob/main/src/naming.adoc
>
> but I still don't see B there. Do you see B in the table you're
> looking
> at?
>
> >
> > The proposed B specification does not make any remarks about the
> > ordering in the ISA definition string. [1] I would worry there
> > would be
> > a lot of software churn if this ordering were to be changed.
>
> The ordering shouldn't change, but I can't see where it's documented
> (beyond the B chapter coming after the C chapter).
I'm using table 27.1 in the published PDF which is the PDF in this
release:
https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
It looks like it was removed in this commit (which is a set of
backports):
https://github.com/riscv/riscv-isa-manual/commit/6ecd735338241583d53396b7065eab7c9ace68aa
Cheers,
Rob
>
> Thanks,
> drew
Re: [PATCH 1/3] target/riscv: Add infrastructure for 'B' MISA extension, Andrew Jones, 2024/01/11
[PATCH 2/3] target/riscv: Add step to validate 'B' extension, Rob Bradford, 2024/01/09
[PATCH 3/3] target/riscv: Enable 'B' extension on max CPU type, Rob Bradford, 2024/01/09