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From: | Richard Henderson |
Subject: | Re: [PATCH v4 3/6] target/riscv: Add helper functions to calculate current number of masked bits for pointer masking |
Date: | Sat, 20 Jan 2024 18:37:27 +1100 |
User-agent: | Mozilla Thunderbird |
On 1/19/24 09:40, Deepak Gupta wrote:
On Thu, Jan 18, 2024 at 12:50 PM Richard Henderson <richard.henderson@linaro.org> wrote:At some point pointer masking will be in hardware, and the kernel will gain support for it, and there will likely be a prctl() added for it. At the point the kernel finalizes the API, you will be able to enable pointer masking for qemu-user.I am sure I am missing some important detail here, BUT... How is it different from aarch64 "top byte ignore".
It is very similar, yes.
I think commit: 16c8497 enables top byte ignore for user pointers and by default for qemu-user for aarch64 target.
Not quite, no. commit 0e0c030c681730f3ec55ba3b223b608a8f3e8282 Author: Richard Henderson <richard.henderson@linaro.org> Date: Fri Feb 12 10:48:51 2021 -0800 linux-user/aarch64: Implement PR_TAGGED_ADDR_ENABLE is more relevant.
IIRC, user <--> kernel abi is only needed for pointers that are passed to the kernel.
It is also needed to *enable* pointer masking at all.For aarch64, TBI has been enabled for user-space since the beginning, but that is not true for riscv. Therefore there will be a need for a syscall to opt in and enable pointer masking.
And in the case of qemu-user, we are talking about the host kernel.
No, we are not. We are always emulating the guest kernel. r~
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