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[PATCH v2 1/2] target/riscv: Register vendors CSR
From: |
LIU Zhiwei |
Subject: |
[PATCH v2 1/2] target/riscv: Register vendors CSR |
Date: |
Sun, 4 Feb 2024 13:42:27 +0800 |
riscv specification allows custom CSRs in decode area. So we should
register all vendor CSRs in cpu realize stage.
Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
---
1) Use int index to quiet the Werror for "i < 0".
---
target/riscv/cpu.c | 3 +++
target/riscv/tcg/tcg-cpu.c | 18 ++++++++++++++++++
target/riscv/tcg/tcg-cpu.h | 1 +
3 files changed, 22 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8cbfc7e781..2dcbc9ff32 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -1113,6 +1113,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (tcg_enabled()) {
+ riscv_tcg_cpu_register_vendor_csr(cpu);
+ }
riscv_cpu_register_gdb_regs_for_features(cs);
#ifndef CONFIG_USER_ONLY
diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 994ca1cdf9..559bf373f3 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -871,6 +871,24 @@ static void riscv_cpu_validate_profiles(RISCVCPU *cpu)
}
}
+void riscv_tcg_cpu_register_vendor_csr(RISCVCPU *cpu)
+{
+ static const struct {
+ bool (*guard_func)(const RISCVCPUConfig *);
+ riscv_csr_operations *csr_ops;
+ } vendors[] = {
+ };
+ for (int i = 0; i < ARRAY_SIZE(vendors); ++i) {
+ if (!vendors[i].guard_func(&cpu->cfg)) {
+ continue;
+ }
+ for (size_t j = 0; j < CSR_TABLE_SIZE &&
+ vendors[i].csr_ops[j].name; j++) {
+ csr_ops[j] = vendors[i].csr_ops[j];
+ }
+ }
+}
+
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
{
CPURISCVState *env = &cpu->env;
diff --git a/target/riscv/tcg/tcg-cpu.h b/target/riscv/tcg/tcg-cpu.h
index f7b32417f8..3daaebf4fb 100644
--- a/target/riscv/tcg/tcg-cpu.h
+++ b/target/riscv/tcg/tcg-cpu.h
@@ -25,5 +25,6 @@
void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp);
void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error **errp);
bool riscv_cpu_tcg_compatible(RISCVCPU *cpu);
+void riscv_tcg_cpu_register_vendor_csr(RISCVCPU *cpu);
#endif
--
2.25.1