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[PATCH 47/65] target/riscv: Add single-width floating-point/integer type
From: |
Huang Tao |
Subject: |
[PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert instructions for XTheadVector |
Date: |
Fri, 12 Apr 2024 15:37:17 +0800 |
Compared to RVV1.0, XTheadVector lacks .rtz instructions, which specify the
rounding mode of rounding to zero.
Except of lack of similar instructions, the instructions have the same function
as RVV1.0. Overall there are only general differences between XTheadVector and
RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 13 ++++++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 10 +++---
target/riscv/xtheadvector_helper.c | 33 +++++++++++++++++++
3 files changed, 52 insertions(+), 4 deletions(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 886655899e..18640c4a1e 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2197,3 +2197,16 @@ DEF_HELPER_5(th_vfclass_v_d, void, ptr, ptr, ptr, env,
i32)
DEF_HELPER_6(th_vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(th_vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(th_vfcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_x_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index 8e928febb7..27a06c2cac 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2191,16 +2191,18 @@ static bool trans_th_vfmv_v_f(DisasContext *s,
arg_th_vfmv_v_f *a)
return false;
}
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+GEN_OPFV_TRANS_TH(th_vfcvt_xu_f_v, opfv_check_th)
+GEN_OPFV_TRANS_TH(th_vfcvt_x_f_v, opfv_check_th)
+GEN_OPFV_TRANS_TH(th_vfcvt_f_xu_v, opfv_check_th)
+GEN_OPFV_TRANS_TH(th_vfcvt_f_x_v, opfv_check_th)
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_vfcvt_xu_f_v)
-TH_TRANS_STUB(th_vfcvt_x_f_v)
-TH_TRANS_STUB(th_vfcvt_f_xu_v)
-TH_TRANS_STUB(th_vfcvt_f_x_v)
TH_TRANS_STUB(th_vfwcvt_xu_f_v)
TH_TRANS_STUB(th_vfwcvt_x_f_v)
TH_TRANS_STUB(th_vfwcvt_f_xu_v)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index e31e13dff3..7e98c1ead2 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3205,3 +3205,36 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void
*vs2, \
GEN_VFMERGE_VF_TH(th_vfmerge_vfm_h, int16_t, H2, clearh_th)
GEN_VFMERGE_VF_TH(th_vfmerge_vfm_w, int32_t, H4, clearl_th)
GEN_VFMERGE_VF_TH(th_vfmerge_vfm_d, int64_t, H8, clearq_th)
+
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
+THCALL(TH_OPFVV1, th_vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
+THCALL(TH_OPFVV1, th_vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
+THCALL(TH_OPFVV1, th_vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
+GEN_TH_V_ENV(th_vfcvt_xu_f_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_xu_f_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_xu_f_v_d, 8, 8, clearq_th)
+
+/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
+THCALL(TH_OPFVV1, th_vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
+THCALL(TH_OPFVV1, th_vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
+THCALL(TH_OPFVV1, th_vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
+GEN_TH_V_ENV(th_vfcvt_x_f_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_x_f_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_x_f_v_d, 8, 8, clearq_th)
+
+/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
+THCALL(TH_OPFVV1, th_vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
+THCALL(TH_OPFVV1, th_vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
+THCALL(TH_OPFVV1, th_vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
+GEN_TH_V_ENV(th_vfcvt_f_xu_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_f_xu_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_f_xu_v_d, 8, 8, clearq_th)
+
+/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
+THCALL(TH_OPFVV1, th_vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
+THCALL(TH_OPFVV1, th_vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
+THCALL(TH_OPFVV1, th_vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
+GEN_TH_V_ENV(th_vfcvt_f_x_v_h, 2, 2, clearh_th)
+GEN_TH_V_ENV(th_vfcvt_f_x_v_w, 4, 4, clearl_th)
+GEN_TH_V_ENV(th_vfcvt_f_x_v_d, 8, 8, clearq_th)
--
2.44.0
- [PATCH 37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector, (continued)
- [PATCH 37/65] target/riscv: Add widening floating-point add/sub instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 38/65] target/riscv: Add single-width floating-point multiply/divide instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 39/65] target/riscv: Add widening floating-point multiply instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 40/65] target/riscv: Add single-width floating-point fused multiply-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 41/65] target/riscv: Add widening floating-point fused mul-add instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 42/65] target/riscv: Add floating-pointing square-root instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 43/65] target/riscv: Add floating-point MIN/MAX instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 44/65] target/riscv: Add floating-point sign-injection instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 45/65] target/riscv: Add floating-point compare instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 46/65] target/riscv: Add floating-point classify and merge instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 47/65] target/riscv: Add single-width floating-point/integer type-convert instructions for XTheadVector,
Huang Tao <=
- [PATCH 48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 49/65] target/riscv: Add narrowing floating-point/integer type-convert instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 50/65] target/riscv: Add single-width integer reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 51/65] target/riscv: Add widening integer reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 54/65] target/riscv: Add mask-register logical instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 55/65] target/riscv: Add vector mask population count vmpopc for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 56/65] target/riscv: Add th.vmfirst.m for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector, Huang Tao, 2024/04/12