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[PATCH 58/65] target/riscv: Add vector iota instruction for XTheadVector
From: |
Huang Tao |
Subject: |
[PATCH 58/65] target/riscv: Add vector iota instruction for XTheadVector |
Date: |
Fri, 12 Apr 2024 15:37:28 +0800 |
The instruction has the same function as RVV1.0. Overall there are only
general differences between XTheadVector and RVV1.0.
Signed-off-by: Huang Tao <eric.huang@linux.alibaba.com>
---
target/riscv/helper.h | 5 ++++
.../riscv/insn_trans/trans_xtheadvector.c.inc | 29 +++++++++++++++++-
target/riscv/xtheadvector_helper.c | 30 +++++++++++++++++++
3 files changed, 63 insertions(+), 1 deletion(-)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 90a1ff2601..a1c85e5254 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -2306,3 +2306,8 @@ DEF_HELPER_4(th_vmfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(th_vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(th_vmsif_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(th_vmsof_m, void, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_5(th_viota_m_b, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_viota_m_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_viota_m_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(th_viota_m_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn_trans/trans_xtheadvector.c.inc
b/target/riscv/insn_trans/trans_xtheadvector.c.inc
index d41c691c31..93f4ee4a12 100644
--- a/target/riscv/insn_trans/trans_xtheadvector.c.inc
+++ b/target/riscv/insn_trans/trans_xtheadvector.c.inc
@@ -2534,13 +2534,40 @@ GEN_M_TRANS_TH(th_vmsbf_m)
GEN_M_TRANS_TH(th_vmsif_m)
GEN_M_TRANS_TH(th_vmsof_m)
+/* Vector Iota Instruction */
+static bool trans_th_viota_m(DisasContext *s, arg_th_viota_m *a)
+{
+ if (require_xtheadvector(s) &&
+ vext_check_isa_ill(s) &&
+ th_check_reg(s, a->rd, false) &&
+ th_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
+ (a->vm != 0 || a->rd != 0) &&
+ s->vstart_eq_zero) {
+ uint32_t data = 0;
+
+ data = FIELD_DP32(data, VDATA_TH, MLEN, s->mlen);
+ data = FIELD_DP32(data, VDATA_TH, VM, a->vm);
+ data = FIELD_DP32(data, VDATA_TH, LMUL, s->lmul);
+ static gen_helper_gvec_3_ptr * const fns[4] = {
+ gen_helper_th_viota_m_b, gen_helper_th_viota_m_h,
+ gen_helper_th_viota_m_w, gen_helper_th_viota_m_d,
+ };
+ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
+ vreg_ofs(s, a->rs2), tcg_env,
+ s->cfg_ptr->vlenb,
+ s->cfg_ptr->vlenb, data, fns[s->sew]);
+ finalize_rvv_inst(s);
+ return true;
+ }
+ return false;
+}
+
#define TH_TRANS_STUB(NAME) \
static bool trans_##NAME(DisasContext *s, arg_##NAME *a) \
{ \
return require_xtheadvector(s); \
}
-TH_TRANS_STUB(th_viota_m)
TH_TRANS_STUB(th_vid_v)
TH_TRANS_STUB(th_vext_x_v)
TH_TRANS_STUB(th_vmv_s_x)
diff --git a/target/riscv/xtheadvector_helper.c
b/target/riscv/xtheadvector_helper.c
index d4f1665bf3..b0ddb3b307 100644
--- a/target/riscv/xtheadvector_helper.c
+++ b/target/riscv/xtheadvector_helper.c
@@ -3622,3 +3622,33 @@ void HELPER(th_vmsof_m)(void *vd, void *v0, void *vs2,
CPURISCVState *env,
{
vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST);
}
+
+/* Vector Iota Instruction */
+#define GEN_TH_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
+ uint32_t desc) \
+{ \
+ uint32_t mlen = th_mlen(desc); \
+ uint32_t vlmax = (env_archcpu(env)->cfg.vlenb << 3) / mlen; \
+ uint32_t vm = th_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t sum = 0; \
+ int i; \
+ \
+ for (i = env->vstart; i < vl; i++) { \
+ if (!vm && !th_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ *((ETYPE *)vd + H(i)) = sum; \
+ if (th_elem_mask(vs2, mlen, i)) { \
+ sum++; \
+ } \
+ } \
+ env->vstart = 0; \
+ CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
+}
+
+GEN_TH_VIOTA_M(th_viota_m_b, uint8_t, H1, clearb_th)
+GEN_TH_VIOTA_M(th_viota_m_h, uint16_t, H2, clearh_th)
+GEN_TH_VIOTA_M(th_viota_m_w, uint32_t, H4, clearl_th)
+GEN_TH_VIOTA_M(th_viota_m_d, uint64_t, H8, clearq_th)
--
2.44.0
- [PATCH 48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector, (continued)
- [PATCH 48/65] target/riscv: Add widening floating-point/integer type-convert instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 49/65] target/riscv: Add narrowing floating-point/integer type-convert instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 50/65] target/riscv: Add single-width integer reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 51/65] target/riscv: Add widening integer reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 52/65] target/riscv: Add single-width floating-point reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 53/65] target/riscv: Add widening floating-point reduction instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 54/65] target/riscv: Add mask-register logical instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 55/65] target/riscv: Add vector mask population count vmpopc for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 56/65] target/riscv: Add th.vmfirst.m for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 57/65] target/riscv: Add set-X-first mask bit instructrions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 58/65] target/riscv: Add vector iota instruction for XTheadVector,
Huang Tao <=
- [PATCH 59/65] target/riscv: Add vector element index instruction for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 60/65] target/riscv: Add integer extract and scalar move instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 61/65] target/riscv: Add floating-point scalar move instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 62/65] target/riscv: Add vector slide instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 63/65] target/riscv: Add vector register gather instructions for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 64/65] target/riscv: Add vector compress instruction for XTheadVector, Huang Tao, 2024/04/12
- [PATCH 65/65] target/riscv: Enable XTheadVector extension for c906, Huang Tao, 2024/04/12