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Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions |
Date: |
Mon, 29 Apr 2024 13:36:12 +1000 |
On Thu, Mar 28, 2024 at 12:25 PM Jason Chien <jason.chien@sifive.com> wrote:
>
> This patch series adds the support for Zve32x and Zvx64x and makes vector
> registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled.
>
> v2:
> Rebase onto riscv-to-apply.next (commit 385e575).
> v3:
> Spuash patch 2 into patch 1.
> Spuash patch 4 into patch 3.
>
> Jason Chien (3):
> target/riscv: Add support for Zve32x extension
> target/riscv: Add support for Zve64x extension
> target/riscv: Relax vector register check in RISCV gdbstub
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> target/riscv/cpu.c | 4 +++
> target/riscv/cpu_cfg.h | 2 ++
> target/riscv/cpu_helper.c | 2 +-
> target/riscv/csr.c | 2 +-
> target/riscv/gdbstub.c | 2 +-
> target/riscv/insn_trans/trans_rvv.c.inc | 4 +--
> target/riscv/tcg/tcg-cpu.c | 33 ++++++++++++++-----------
> 7 files changed, 30 insertions(+), 19 deletions(-)
>
> --
> 2.43.2
>
>