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[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0
From: |
Fea.Wang |
Subject: |
[PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0 |
Date: |
Fri, 10 May 2024 14:58:53 +0800 |
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in
SMSTATEEN0 that controls access to the hedeleg.
Signed-off-by: Fea.Wang <fea.wang@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/cpu_bits.h | 1 +
target/riscv/csr.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 74318a925c..28bd3fb0b4 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -315,6 +315,7 @@
#define SMSTATEEN0_CS (1ULL << 0)
#define SMSTATEEN0_FCSR (1ULL << 1)
#define SMSTATEEN0_JVT (1ULL << 2)
+#define SMSTATEEN0_P1P13 (1ULL << 56)
#define SMSTATEEN0_HSCONTXT (1ULL << 57)
#define SMSTATEEN0_IMSIC (1ULL << 58)
#define SMSTATEEN0_AIA (1ULL << 59)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6b460ee0e8..d844ce770e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2248,6 +2248,11 @@ static RISCVException write_mstateen0(CPURISCVState
*env, int csrno,
wr_mask |= SMSTATEEN0_FCSR;
}
+ RISCVCPU *cpu = env_archcpu(env);
+ if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+ wr_mask |= SMSTATEEN0_P1P13;
+ }
+
return write_mstateen(env, csrno, wr_mask, new_val);
}
@@ -2283,6 +2288,11 @@ static RISCVException write_mstateen0h(CPURISCVState
*env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
+ RISCVCPU *cpu = env_archcpu(env);
+ if (cpu->env.priv_ver >= PRIV_VERSION_1_13_0) {
+ wr_mask |= SMSTATEEN0_P1P13;
+ }
+
return write_mstateenh(env, csrno, wr_mask, new_val);
}
--
2.34.1
- [PATCH 0/5] target/riscv: Support RISC-V privilege 1.13 spec, Fea.Wang, 2024/05/10
- [PATCH 1/5] target/riscv: Reuse the conversion function of priv_spec and string, Fea.Wang, 2024/05/10
- [PATCH 2/5] target/riscv: Support the version for ss1p13, Fea.Wang, 2024/05/10
- [PATCH 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0,
Fea.Wang <=
- [PATCH 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Fea.Wang, 2024/05/10
- [PATCH 5/5] target/riscv: Reserve exception codes for sw-check and hw-err, Fea.Wang, 2024/05/10