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[RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec
From: |
Fea.Wang |
Subject: |
[RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec |
Date: |
Wed, 15 May 2024 16:05:57 +0800 |
Based on the change log for the RISC-V privilege 1.13 spec, add the
support for ss1p13.
Ref:https://github.com/riscv/riscv-isa-manual/blob/a7d93c9/src/priv-preface.adoc?plain=1#L40-L72
Lists what to do without clarification or document format.
* Redefined misa.MXL to be read-only, making MXLEN a constant.(Skip,
implementation ignored)
* Added the constraint that SXLEN≥UXLEN.(Skip, implementation ignored)
* Defined the misa.V field to reflect that the V extension has been
implemented.(Skip, existed)
* Defined the RV32-only medelegh and hedelegh CSRs.(Done in these patches)
* Defined the misaligned atomicity granule PMA, superseding the proposed Zam
extension..(Skip, implementation ignored)
* Allocated interrupt 13 for Sscofpmf LCOFI interrupt.(Skip, existed)
* Defined hardware error and software check exception codes.(Done in these
patches)
* Specified synchronization requirements when changing the PBMTE fields in
menvcfg and henvcfg.(Skip, implementation ignored)
* Incorporated Svade and Svadu extension specifications.(Skip, existed)
Fea.Wang (4):
target/riscv: Support the version for ss1p13
target/riscv: Add 'P1P13' bit in SMSTATEEN0
target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32
target/riscv: Reserve exception codes for sw-check and hw-err
Jim Shu (1):
target/riscv: Reuse the conversion function of priv_spec
target/riscv/cpu.c | 8 ++++++--
target/riscv/cpu.h | 5 ++++-
target/riscv/cpu_bits.h | 5 +++++
target/riscv/cpu_cfg.h | 1 +
target/riscv/csr.c | 39 ++++++++++++++++++++++++++++++++++++++
target/riscv/tcg/tcg-cpu.c | 17 ++++++++---------
6 files changed, 63 insertions(+), 12 deletions(-)
--
2.34.1
- [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec,
Fea.Wang <=
- [RESEND PATCH v2 2/5] target/riscv: Support the version for ss1p13, Fea.Wang, 2024/05/15
- [RESEND PATCH v2 1/5] target/riscv: Reuse the conversion function of priv_spec, Fea.Wang, 2024/05/15
- [RESEND PATCH v2 3/5] target/riscv: Add 'P1P13' bit in SMSTATEEN0, Fea.Wang, 2024/05/15
- [RESEND PATCH v2 4/5] target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32, Fea.Wang, 2024/05/15
- [RESEND PATCH v2 5/5] target/riscv: Reserve exception codes for sw-check and hw-err, Fea.Wang, 2024/05/15
- Re: [RESEND PATCH v2 0/5] target/riscv: Support RISC-V privilege 1.13 spec, Daniel Henrique Barboza, 2024/05/27