[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH 0/4] target/riscv: Implement May-Be-Operations(zimop) extension
From: |
LIU Zhiwei |
Subject: |
[PATCH 0/4] target/riscv: Implement May-Be-Operations(zimop) extension |
Date: |
Wed, 22 May 2024 14:29:01 +0800 |
The may be operation means that it has an initial behavior which can be
redefined
by later extensions to perform some other action.
The May-Be-Operations includes two extension: zimop and zcmop. Zimop has 40
instructions, whose initial behavior is writing zero to the destination
register.
Zcmop, which requires the Zca extension, has 8 instructions whose initial
behavior is reading the source register.
The more details on this specifcation is here:
https://github.com/riscv/riscv-isa-manual/blob/main/src/zimop.adoc
LIU Zhiwei (4):
target/riscv: Add zimop extension
disas/riscv: Support zimop disassemble
target/riscv: Add zcmop extension
disas/riscv: Support zcmop disassemble
disas/riscv.c | 123 ++++++++++++++++++++
target/riscv/cpu.c | 4 +
target/riscv/cpu_cfg.h | 2 +
target/riscv/insn16.decode | 1 +
target/riscv/insn32.decode | 11 ++
target/riscv/insn_trans/trans_rvzcmop.c.inc | 29 +++++
target/riscv/insn_trans/trans_rvzimop.c.inc | 37 ++++++
target/riscv/tcg/tcg-cpu.c | 5 +
target/riscv/translate.c | 2 +
9 files changed, 214 insertions(+)
create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvzimop.c.inc
--
2.25.1
- [PATCH 0/4] target/riscv: Implement May-Be-Operations(zimop) extension,
LIU Zhiwei <=