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Re: [PATCH] targer/riscv: Implement Zabha extension
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From: |
Alexandre Ghiti |
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Subject: |
Re: [PATCH] targer/riscv: Implement Zabha extension |
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Date: |
Tue, 28 May 2024 09:10:18 +0200 |
Hi Zhiwei,
On Tue, May 28, 2024 at 8:57 AM LIU Zhiwei <zhiwei_liu@linux.alibaba.com> wrote:
>
> Hi Alexandre,
>
> I have sent the patch set about Zabha before last week.
Sorry I did not check!
>
> fed99165-58da-458c-b68f-a9717fc15034@linux.alibaba.com/T/">https://lore.kernel.org/all/fed99165-58da-458c-b68f-a9717fc15034@linux.alibaba.com/T/
>
> Welcome to review it and give comments.
Sure, I'll do that, your patchset seems more complete than ours.
Thanks,
Alex
>
> Thanks,
> Zhiwei
>
> On 2024/5/28 13:45, Alexandre Ghiti wrote:
> > From: Gianluca Guida <gianluca@rivosinc.com>
> >
> > Add Zabha implementation.
> >
> > Signed-off-by: Gianluca Guida <gianluca@rivosinc.com>
> > Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> > ---
> > target/riscv/cpu.c | 2 +
> > target/riscv/cpu_cfg.h | 1 +
> > target/riscv/insn32.decode | 22 +++
> > target/riscv/insn_trans/trans_rvzabha.c.inc | 149 ++++++++++++++++++++
> > target/riscv/tcg/tcg-cpu.c | 5 +
> > target/riscv/translate.c | 1 +
> > 6 files changed, 180 insertions(+)
> > create mode 100644 target/riscv/insn_trans/trans_rvzabha.c.inc
> >
> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> > index 70d1a527a1..b01f82002b 100644
> > --- a/target/riscv/cpu.c
> > +++ b/target/riscv/cpu.c
> > @@ -116,6 +116,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
> > ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
> > ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_11),
> > ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
> > + ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_12_0, ext_zabha),
> > ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
> > ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
> > ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
> > @@ -1464,6 +1465,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] =
> > {
> > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
> > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
> > MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
> > + MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false),
> > MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
> > MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
> > MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
> > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h
> > index d36c416ef0..7f614da4e2 100644
> > --- a/target/riscv/cpu_cfg.h
> > +++ b/target/riscv/cpu_cfg.h
> > @@ -81,6 +81,7 @@ struct RISCVCPUConfig {
> > bool ext_svvptc;
> > bool ext_zdinx;
> > bool ext_zaamo;
> > + bool ext_zabha;
> > bool ext_zacas;
> > bool ext_zalrsc;
> > bool ext_zawrs;
> > diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> > index f22df04cfd..6d7726120f 100644
> > --- a/target/riscv/insn32.decode
> > +++ b/target/riscv/insn32.decode
> > @@ -1010,3 +1010,25 @@ amocas_w 00101 . . ..... ..... 010 ..... 0101111
> > @atom_st
> > amocas_d 00101 . . ..... ..... 011 ..... 0101111 @atom_st
> > # *** RV64 Zacas Standard Extension ***
> > amocas_q 00101 . . ..... ..... 100 ..... 0101111 @atom_st
> > +
> > +# *** Zabha Standard Extension ***
> > +amoswap_b 00001 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amoadd_b 00000 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amoxor_b 00100 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amoand_b 01100 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amoor_b 01000 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amomin_b 10000 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amomax_b 10100 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amominu_b 11000 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amomaxu_b 11100 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amocas_b 00101 . . ..... ..... 000 ..... 0101111 @atom_st
> > +amoswap_h 00001 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amoadd_h 00000 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amoxor_h 00100 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amoand_h 01100 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amoor_h 01000 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amomin_h 10000 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amomax_h 10100 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amominu_h 11000 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amomaxu_h 11100 . . ..... ..... 001 ..... 0101111 @atom_st
> > +amocas_h 00101 . . ..... ..... 001 ..... 0101111 @atom_st
> > diff --git a/target/riscv/insn_trans/trans_rvzabha.c.inc
> > b/target/riscv/insn_trans/trans_rvzabha.c.inc
> > new file mode 100644
> > index 0000000000..74f43bb95a
> > --- /dev/null
> > +++ b/target/riscv/insn_trans/trans_rvzabha.c.inc
> > @@ -0,0 +1,149 @@
> > +/*
> > + * RISC-V translation routines for the Zabha Standard Extension.
> > + *
> > + * Copyright (c) 2023 Rivos Inc.
> > + *
> > + * This program is free software; you can redistribute it and/or modify it
> > + * under the terms and conditions of the GNU General Public License,
> > + * version 2 or later, as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope it will be useful, but WITHOUT
> > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
> > for
> > + * more details.
> > + *
> > + * You should have received a copy of the GNU General Public License along
> > with
> > + * this program. If not, see <http://www.gnu.org/licenses/>.
> > + */
> > +
> > +#define REQUIRE_ZABHA(ctx) do { \
> > + if (!ctx->cfg_ptr->ext_zabha) { \
> > + return false; \
> > + } \
> > + } while (0)
> > +
> > +#define REQUIRE_ZABHA_AND_ZACAS(ctx) do { \
> > + if (!ctx->cfg_ptr->ext_zabha || !ctx->cfg_ptr->ext_zacas) { \
> > + return false; \
> > + } \
> > + } while (0)
> > +
> > +static bool trans_amoswap_b(DisasContext *ctx, arg_amoswap_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amoswap_h(DisasContext *ctx, arg_amoswap_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_xchg_tl, (MO_ALIGN | MO_TESW));
> > +}
> > +
> > +static bool trans_amoadd_b(DisasContext *ctx, arg_amoadd_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amoadd_h(DisasContext *ctx, arg_amoadd_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_add_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amoxor_b(DisasContext *ctx, arg_amoxor_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amoxor_h(DisasContext *ctx, arg_amoxor_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_xor_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amoand_b(DisasContext *ctx, arg_amoand_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amoand_h(DisasContext *ctx, arg_amoand_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_and_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amoor_b(DisasContext *ctx, arg_amoor_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amoor_h(DisasContext *ctx, arg_amoor_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_or_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amomin_b(DisasContext *ctx, arg_amomin_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amomin_h(DisasContext *ctx, arg_amomin_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smin_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amomax_b(DisasContext *ctx, arg_amomax_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amomax_h(DisasContext *ctx, arg_amomax_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_smax_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amominu_b(DisasContext *ctx, arg_amominu_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amominu_h(DisasContext *ctx, arg_amominu_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umin_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amomaxu_b(DisasContext *ctx, arg_amomaxu_b *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, MO_SB);
> > +}
> > +
> > +static bool trans_amomaxu_h(DisasContext *ctx, arg_amomaxu_h *a)
> > +{
> > + REQUIRE_ZABHA(ctx);
> > + return gen_amo(ctx, a, &tcg_gen_atomic_fetch_umax_tl, (MO_ALIGN |
> > MO_TESW));
> > +}
> > +
> > +static bool trans_amocas_b(DisasContext *ctx, arg_amocas_b *a)
> > +{
> > + REQUIRE_ZABHA_AND_ZACAS(ctx);
> > + return gen_cmpxchg(ctx, a, MO_SB);
> > +}
> > +
> > +static bool trans_amocas_h(DisasContext *ctx, arg_amocas_h *a)
> > +{
> > + REQUIRE_ZABHA_AND_ZACAS(ctx);
> > + return gen_cmpxchg(ctx, a, (MO_ALIGN | MO_TESW));
> > +}
> > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> > index b5b95e052d..25a57bac0f 100644
> > --- a/target/riscv/tcg/tcg-cpu.c
> > +++ b/target/riscv/tcg/tcg-cpu.c
> > @@ -456,6 +456,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> > Error **errp)
> > return;
> > }
> >
> > + if ((cpu->cfg.ext_zabha) && !riscv_has_ext(env, RVA)) {
> > + error_setg(errp, "Zabha extension requires A extension");
> > + return;
> > + }
> > +
> > if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
> > error_setg(errp, "Zawrs extension requires A extension");
> > return;
> > diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> > index 9ff09ebdb6..1e128711db 100644
> > --- a/target/riscv/translate.c
> > +++ b/target/riscv/translate.c
> > @@ -1097,6 +1097,7 @@ static uint32_t opcode_at(DisasContextBase *dcbase,
> > target_ulong pc)
> > #include "insn_trans/trans_rvb.c.inc"
> > #include "insn_trans/trans_rvzicond.c.inc"
> > #include "insn_trans/trans_rvzacas.c.inc"
> > +#include "insn_trans/trans_rvzabha.c.inc"
> > #include "insn_trans/trans_rvzawrs.c.inc"
> > #include "insn_trans/trans_rvzicbo.c.inc"
> > #include "insn_trans/trans_rvzfa.c.inc"