Re: [PATCH v2 0/7] target/riscv: Expose RV32 cpu to RV64 QEMU

[Philippe Mathieu-Daudé]

Hi,

On 3/7/24 14:34, LIU Zhiwei wrote:
> From: TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
>
> This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
> qemu-system-riscv64 can directly boot a RV32 Linux.
>
> This patch set has been tested with 6.9.0 Linux Image.
> And add an avocado test in tests/avocado.
>
> v2:
>    Remove the line that was inadvertently left in PATCH v1 4/6.
>    Add an avocado test.
>
> v1:
>    https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
>
> TANG Tiancheng (7):
>    target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
>    target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
>    target/riscv: Correct SXL return value for RV32 in RV64 QEMU
>    target/riscv: Detect sxl to set bit width for RV32 in RV64
>    target/riscv: Correct mcause/scause bit width for RV32 in RV64 QEMU
>    target/riscv: Enable RV32 CPU support in RV64 QEMU
>    tests/avocado: Add an avocado test for riscv64

On what is that based? It fails when applying:

Applying: target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI
Applying: target/riscv: Adjust PMP size for no-MMU RV64 QEMU running RV32
Applying: target/riscv: Correct SXL return value for RV32 in RV64 QEMU
Applying: target/riscv: Detect sxl to set bit width for RV32 in RV64
Applying: target/riscv: Correct mcause/scause bit width for RV32 in RV64 
QEMU
Applying: target/riscv: Enable RV32 CPU support in RV64 QEMU
Patch failed at 0006 target/riscv: Enable RV32 CPU support in RV64 QEMU
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
error: patch failed: configs/targets/riscv64-softmmu.mak:1
error: configs/targets/riscv64-softmmu.mak: patch does not apply
hint: Use 'git am --show-current-patch=diff' to see the failed patch