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[PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main
From: |
Ajeet Singh |
Subject: |
[PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop |
Date: |
Tue, 17 Sep 2024 01:51:03 +1000 |
From: Mark Corbin <mark@dibsco.co.uk>
Added the initial implementation for RISC-V CPU initialization and main
loop. This includes setting up the general-purpose registers and
program counter based on the provided target architecture definitions.
Signed-off-by: Mark Corbin <mark@dibsco.co.uk>
Signed-off-by: Ajeet Singh <itachis@FreeBSD.org>
Co-authored-by: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
bsd-user/riscv/target_arch_cpu.h | 40 ++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
create mode 100644 bsd-user/riscv/target_arch_cpu.h
diff --git a/bsd-user/riscv/target_arch_cpu.h b/bsd-user/riscv/target_arch_cpu.h
new file mode 100644
index 0000000000..f8d85e01ad
--- /dev/null
+++ b/bsd-user/riscv/target_arch_cpu.h
@@ -0,0 +1,40 @@
+/*
+ * RISC-V CPU init and loop
+ *
+ * Copyright (c) 2019 Mark Corbin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef TARGET_ARCH_CPU_H
+#define TARGET_ARCH_CPU_H
+
+#include "target_arch.h"
+#include "signal-common.h"
+
+#define TARGET_DEFAULT_CPU_MODEL "max"
+
+static inline void target_cpu_init(CPURISCVState *env,
+ struct target_pt_regs *regs)
+{
+ int i;
+
+ for (i = 1; i < 32; i++) {
+ env->gpr[i] = regs->regs[i];
+ }
+
+ env->pc = regs->sepc;
+}
+
+#endif /* TARGET_ARCH_CPU_H */
--
2.34.1
- [PATCH v7 00/17] bsd-user: Comprehensive RISCV Support, Ajeet Singh, 2024/09/16
- [PATCH v7 01/17] bsd-user: Implement RISC-V CPU initialization and main loop,
Ajeet Singh <=
- [PATCH v7 04/17] bsd-user: Implement RISC-V TLS register setup, Ajeet Singh, 2024/09/16
- [PATCH v7 07/17] bsd-user: Add RISC-V signal trampoline setup function, Ajeet Singh, 2024/09/16
- [PATCH v7 16/17] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV, Ajeet Singh, 2024/09/16
- [PATCH v7 14/17] bsd-user: Implement RISC-V signal trampoline setup functions, Ajeet Singh, 2024/09/16
- [PATCH v7 17/17] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files, Ajeet Singh, 2024/09/16
- [PATCH v7 15/17] bsd-user: Implement 'get_mcontext' for RISC-V, Ajeet Singh, 2024/09/16
- [PATCH v7 02/17] bsd-user: Add RISC-V CPU execution loop and syscall handling, Ajeet Singh, 2024/09/16
- [PATCH v7 03/17] bsd-user: Implement RISC-V CPU register cloning and reset functions, Ajeet Singh, 2024/09/16
- [PATCH v7 05/17] bsd-user: Add RISC-V ELF definitions and hardware capability detection, Ajeet Singh, 2024/09/16
- [PATCH v7 06/17] bsd-user: Define RISC-V register structures and register copying, Ajeet Singh, 2024/09/16