[RFC v5 0/1] target/riscv: rvv: reduce the overhead for simple RISC-V vector.

[Paolo Savini]

The version 5 of the patch set splits the patches into independent submissions
so to simplify the review process.

Previous versions:
- v1: 
https://lore.kernel.org/all/20240717153040.11073-1-paolo.savini@embecosm.com/
- v2: 
https://lore.kernel.org/all/20241002135708.99146-1-paolo.savini@embecosm.com/
- v3: 
https://lore.kernel.org/all/20241014220153.196183-1-paolo.savini@embecosm.com/
- v4: 
https://lore.kernel.org/all/20241029194348.59574-1-paolo.savini@embecosm.com/

Cc: Richard Handerson <richard.henderson@linaro.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <alistair.francis@wdc.com>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Weiwei Li <liwei1518@gmail.com>
Cc: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Cc: Liu Zhiwei <zhiwei_liu@linux.alibaba.com>
Cc: Helene Chelin <helene.chelin@embecosm.com>
Cc: Nathan Egge <negge@google.com>
Cc: Max Chou <max.chou@sifive.com>

Helene CHELIN (1):
  target/riscv: rvv: reduce the overhead for simple RISC-V vector
    unit-stride loads and stores

 target/riscv/vector_helper.c | 47 ++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

-- 
2.34.1