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[PATCH v9 5/6] target/riscv: Add Smrnmi cpu extension
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From: |
frank . chang |
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Subject: |
[PATCH v9 5/6] target/riscv: Add Smrnmi cpu extension |
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Date: |
Fri, 22 Nov 2024 11:22:16 +0800 |
From: Tommy Wu <tommy.wu@sifive.com>
This adds the properties for ISA extension Smrnmi.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Signed-off-by: Tommy Wu <tommy.wu@sifive.com>
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index b402d8545b..6c91464a00 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -186,6 +186,7 @@ const RISCVIsaExtData isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
+ ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi),
ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
@@ -1516,6 +1517,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
+ MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false),
MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
--
2.34.1
- [PATCH v9 0/6] Add Smrnmi support, frank . chang, 2024/11/21
- [PATCH v9 1/6] target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig, frank . chang, 2024/11/21
- [PATCH v9 2/6] target/riscv: Add Smrnmi CSRs, frank . chang, 2024/11/21
- [PATCH v9 3/6] target/riscv: Handle Smrnmi interrupt and exception, frank . chang, 2024/11/21
- [PATCH v9 4/6] target/riscv: Add Smrnmi mnret instruction, frank . chang, 2024/11/21
- [PATCH v9 5/6] target/riscv: Add Smrnmi cpu extension,
frank . chang <=
- [PATCH v9 6/6] target/riscv: Add Zicfilp support for Smrnmi, frank . chang, 2024/11/21