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[PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_fr
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs |
Date: |
Mon, 17 May 2021 12:51:23 +0200 |
To be able to later extract the cpu_get_phys_page_debug() and
cpu_asidx_from_attrs() handlers from CPUClass, un-inline them
from "hw/core/cpu.h".
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
include/hw/core/cpu.h | 33 ++++-----------------------------
hw/core/cpu-sysemu.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 36 insertions(+), 29 deletions(-)
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
index d45f78290e0..df495287850 100644
--- a/include/hw/core/cpu.h
+++ b/include/hw/core/cpu.h
@@ -586,18 +586,8 @@ void cpu_dump_statistics(CPUState *cpu, int flags);
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
- MemTxAttrs *attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
-
- if (cc->get_phys_page_attrs_debug) {
- return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
- }
- /* Fallback for CPUs which don't implement the _attrs_ hook */
- *attrs = MEMTXATTRS_UNSPECIFIED;
- return cc->get_phys_page_debug(cpu, addr);
-}
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs);
/**
* cpu_get_phys_page_debug:
@@ -609,12 +599,7 @@ static inline hwaddr
cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
*
* Returns: Corresponding physical page address or -1 if no page found.
*/
-static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
-{
- MemTxAttrs attrs = {};
-
- return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
-}
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
/** cpu_asidx_from_attrs:
* @cpu: CPU
@@ -623,17 +608,7 @@ static inline hwaddr cpu_get_phys_page_debug(CPUState
*cpu, vaddr addr)
* Returns the address space index specifying the CPU AddressSpace
* to use for a memory access with the given transaction attributes.
*/
-static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
-{
- CPUClass *cc = CPU_GET_CLASS(cpu);
- int ret = 0;
-
- if (cc->asidx_from_attrs) {
- ret = cc->asidx_from_attrs(cpu, attrs);
- assert(ret < cpu->num_ases && ret >= 0);
- }
- return ret;
-}
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs);
#endif /* CONFIG_USER_ONLY */
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
index f517ef5d460..fe90dde8681 100644
--- a/hw/core/cpu-sysemu.c
+++ b/hw/core/cpu-sysemu.c
@@ -22,6 +22,38 @@
#include "qapi/error.h"
#include "hw/core/cpu.h"
+hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
+ MemTxAttrs *attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+
+ if (cc->get_phys_page_attrs_debug) {
+ return cc->get_phys_page_attrs_debug(cpu, addr, attrs);
+ }
+ /* Fallback for CPUs which don't implement the _attrs_ hook */
+ *attrs = MEMTXATTRS_UNSPECIFIED;
+ return cc->get_phys_page_debug(cpu, addr);
+}
+
+hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
+{
+ MemTxAttrs attrs = {};
+
+ return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs);
+}
+
+int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
+{
+ CPUClass *cc = CPU_GET_CLASS(cpu);
+ int ret = 0;
+
+ if (cc->asidx_from_attrs) {
+ ret = cc->asidx_from_attrs(cpu, attrs);
+ assert(ret < cpu->num_ases && ret >= 0);
+ }
+ return ret;
+}
+
GuestPanicInformation *cpu_get_crash_info(CPUState *cpu)
{
CPUClass *cc = CPU_GET_CLASS(cpu);
--
2.26.3
- [PATCH v7 01/23] NOTFORMERGE target/arm: Restrict MTE code to softmmu, (continued)
- [PATCH v7 03/23] cpu: Restrict target cpu_do_unaligned_access() handlers to sysemu, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 04/23] cpu: Remove duplicated 'sysemu/hw_accel.h' header, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 05/23] cpu: Split as cpu-common / cpu-sysemu, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 06/23] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs,
Philippe Mathieu-Daudé <=
- [PATCH v7 07/23] cpu: Introduce cpu_virtio_is_big_endian(), Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 08/23] cpu: Directly use cpu_write_elf*() fallback handlers in place, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 09/23] cpu: Directly use get_paging_enabled() fallback handlers in place, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 10/23] cpu: Directly use get_memory_mapping() fallback handlers in place, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 11/23] cpu: Assert DeviceClass::vmsd is NULL on user emulation, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 12/23] cpu: Rename CPUClass vmsd -> legacy_vmsd, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 13/23] cpu: Move AVR target vmsd field from CPUClass to DeviceClass, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 14/23] cpu: Introduce SysemuCPUOps structure, Philippe Mathieu-Daudé, 2021/05/17
- [PATCH v7 15/23] cpu: Move CPUClass::vmsd to SysemuCPUOps, Philippe Mathieu-Daudé, 2021/05/17