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[Tinycc-devel] asm syntax of riscv64-asm.c
From: |
noneofyourbusiness |
Subject: |
[Tinycc-devel] asm syntax of riscv64-asm.c |
Date: |
Sun, 11 Aug 2024 01:59:33 +0200 |
8cbbd2b88ac39815c79918610313984cc58db2bf
I propose supporting several syntaxes, at most only those that the RISC-V
specifications themselves showcase.
RV32I V2.1:
jalr x0, ra, 0
"C" extension V2.0:
jalr x0, 0(rs1)
RISC-V ABI V1.0:
jalr ra, ra, 0
jalr t1, t3
currently
jalr x0, 0(rs1)
jalr x0, ra, 0
won't work
P.S. vector examples add more injury to the optional arg problem:
vle32.v v0, (a1)
vle32.v v0, (a1), v0.t
- [Tinycc-devel] asm syntax of riscv64-asm.c,
noneofyourbusiness <=