RE: [avr-gcc-list] Jtag ice

[Svenn-Ivar Svendsen]

> > Was your project using the watchdog reset? That kinda makes it tough
> > to do ICE debugging when the watchdog reset's the system.
>
> At one point, we were sure that this was the problem, but it persisted
> beyond making sure the WDT was disabled.  I should note that we did get
> it to work OK with the ATMega128 at one point; just never the '169.  We
> were using 16MHz parts, early enough that they were delivered by hand
> with unusual markings on the package.  We were also using C++.  Perhaps
> there was an early problem that got straightened out after I gave up.

First thing I would try is to put a capacitor on the TCK line as the help
system suggests.

Also, since things seem to go wrong when writing to PORTB, you could try to
connect a scope (w/ low cap probe) to the JTAG lines to see if the operation
on PORTB generate any kind of noise on the JTAG lines, especially TCK. Also
try to comment out that line to see if it is really causing the problems.
Then you might try to toggle one and one pin, to circle the problem in.

The JTAG port shares pins with ADC channel 4-7. If using these ADC channels
I would disable them to see what happens. However it should not be causing
the problems. Also, if using the internal system clock prescaler to reduce
the system clock, make sure that the resulting clock is still > 4 times that
of the JTAG port.

Svenn-Ivar