[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[avr-gcc-list] Another missed optimization
From: |
Wouter van Gulik |
Subject: |
[avr-gcc-list] Another missed optimization |
Date: |
Thu, 09 Aug 2007 16:20:44 +0200 |
User-agent: |
Thunderbird 2.0.0.6 (Windows/20070728) |
Hi list,
Ok I'll admit this one is rare, but a really annonying one. Since my
application is all in one file I try to optimise the code (and
especially my ISR's) by making heavily used variables reside in lower
part registers. This reduces size a whole lot and speeds up a good bit.
I know that instructions are restricted to handling r16..r31 only. But
this example should not suffer from this.
Why is 0xA load again in r24?
Strange enough gcc does optimise the extra ldi when r is not a explicit
register.
So it seems that the logic for writing register 15 and below is non
optimal? I've seen misses when doing adding as well (I've not tried to
reproduce it yet, will give it another try later)
I used winavr-20070525 (GCC4.1.2) and the following compile options
avr-gcc -S -Os -mmcu=atmega644 test.c
Ok this is the c snippet:
////////////////////////// C ////////////////////////////////////
register unsigned char r asm("r2"); //use only r2..r15
volatile unsigned char dummy; //give the optimizer something to keep
int main(void) {
unsigned char localDummy = dummy;
if(localDummy == 0xA) {
r = localDummy;
}
}
////////////////////////// ASM ////////////////////////////////////
The ASM output:
main:
/* prologue: frame size=0 */
/* prologue end (size=0) */
lds r24,dummy <-- load to localDummy
cpi r24,lo8(10) <-- compare against 0xA
brne .L5 <-- branch
ldi r24,lo8(10) <-- WHY??? it's there allready!
mov r2,r24 <-- mov
.L5:
/* epilogue: frame size=0 */
ret
- [avr-gcc-list] Another missed optimization,
Wouter van Gulik <=