[avr-gcc-list] Explicitly using lower half registers gives non optimal code

[Wouter van Gulik]

Ok I tried adding as well. It's ok when writing something like this:

////////////////////// C ///////////////
register unsigned char r asm("r2");
void foo(unsigned char in) {

    if(in == 0xA) {
        r += in +1 ;
    }
}

You get neat code (but that's because of the optimizer seeing that the 
increment is constant):
////////////////////// ASM ///////////////
        cpi r24,lo8(10)
        brne .L4
        ldi r24,lo8(11)
        add r2,r24
.L4:
        ret



But now try this:
It looks like as if the compiler thinks r2 is in RAM?
I cannot see why r2 should be load in to r24? Is making a variable a 
register giving extra constraints on manipulation (apart from a less 
available instructions?)
I tried different rewrites but all ends up the same. I can image the 
optimizer incrementing "in" before adding it to "r". But I can't make 
sense of this.

////////////////////// C ///////////////
register unsigned char r asm("r2");
void foo(unsigned char in, unsigned char in2) {

    if(in == in2) {
        r += in +1 ;
    }

////////////////////// ASM ///////////////
        mov r25,r24                     << WHY?
        cp r24,r22
        brne .L4
        mov r24,r2                      << WHY?? (tmp = r2)
        subi r24,lo8(-(1))              << tmp++
        mov r2,r25                      << r2 = in1
        add r2,r24                      << r2 += tmp
.L4:
        ret

This last part could have been:
        brne .L4
        inc r24 (or r2)
        add r2, r24


Greetings


Wouter