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[Commit-gnuradio] r4952 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
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Subject: |
[Commit-gnuradio] r4952 - in gnuradio/branches/developers/matt/u2f/opencores: . aemb aemb/CVS aemb/rtl aemb/rtl/CVS aemb/rtl/verilog aemb/rtl/verilog/CVS aemb/sim aemb/sim/CVS aemb/sw aemb/sw/CVS aemb/sw/c aemb/sw/c/CVS ethernet_tri_mode/CVS ethernet_tri_mode/bench/CVS ethernet_tri_mode/rtl/CVS ethernet_tri_mode/rtl/verilog/CVS ethernet_tri_mode/rtl/verilog/TECH/CVS ethernet_tri_mode/sim/CVS ethernet_tri_mode/sim/rtl_sim/CVS ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS i2c/CVS i2c/bench/CVS i2c/doc/CVS i2c/rtl/CVS i2c/sim/CVS i2c/sim/i2c_verilog/CVS i2c/sim/i2c_verilog/run/CVS i2c/software/CVS spi/CVS spi/bench/CVS spi/doc/CVS spi/rtl/CVS spi/sim/CVS spi/sim/rtl_sim/CVS spi_boot/CVS spi_boot/bench/CVS spi_boot/doc/CVS spi_boot/rtl/CVS spi_boot/rtl/vhdl/CVS spi_boot/sim/CVS spi_boot/sw/CVS wb_conbus/CVS wb_conbus/bench/CVS wb_conbus/rtl/CVS |
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Date: |
Wed, 11 Apr 2007 14:59:37 -0600 (MDT) |
Author: matt
Date: 2007-04-11 14:59:34 -0600 (Wed, 11 Apr 2007)
New Revision: 4952
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/
gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/
gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries.Log
gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Repository
gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Root
gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Template
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Repository
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Root
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Template
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Repository
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Root
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Template
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_testbench.v
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Repository
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Root
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Template
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Repository
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Root
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Template
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Repository
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Root
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Template
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/bench/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/doc/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/rtl/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/i2c/software/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi/bench/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi/doc/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi/rtl/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi/sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi/sim/rtl_sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/bench/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/doc/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/vhdl/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sim/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sw/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/bench/CVS/Entries
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/CVS/Entries
Log:
aeMB Microblaze compatible core as of 4/11/07 plus latest versions of some
other stuff
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,5 @@
+D/doc////
+D/rtl////
+D/sim////
+D/sw////
+D/syn////
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries.Log
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries.Log
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Entries.Log
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,2 @@
+R D/syn////
+R D/doc////
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Repository
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Repository
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Repository
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+aemb
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Root
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Root
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Root
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+:pserver:address@hidden:/cvsroot/anonymous
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/CVS/Template
===================================================================
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Entries
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+D/verilog////
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Repository
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Repository
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Repository
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+aemb/rtl
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Root
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Root
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Root
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+:pserver:address@hidden:/cvsroot/anonymous
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/CVS/Template
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,8 @@
+/aeMB_aslu.v/1.4/Wed Apr 11 06:30:44 2007//
+/aeMB_control.v/1.3/Wed Apr 11 06:30:44 2007//
+/aeMB_core.v/1.3/Wed Apr 11 06:30:44 2007//
+/aeMB_decode.v/1.4/Wed Apr 11 06:30:44 2007//
+/aeMB_fetch.v/1.3/Wed Apr 11 06:30:44 2007//
+/aeMB_testbench.v/1.4/Wed Apr 11 06:30:44 2007//
+/aeMB_regfile.v/1.7/Wed Apr 11 20:57:31 2007//
+D
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Repository
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Repository
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Repository
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+aemb/rtl/verilog
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Root
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Root
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Root
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+:pserver:address@hidden:/cvsroot/anonymous
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/CVS/Template
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_aslu.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,194 @@
+/*
+ * $Id: aeMB_aslu.v,v 1.4 2007/04/11 04:30:43 sybreon Exp $
+ *
+ * AEMB Arithmetic Shift Logic Unit
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Arithmetic, shift and logic execution unit
+ *
+ * HISTORY
+ * $Log: aeMB_aslu.v,v $
+ * Revision 1.4 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.3 2007/04/04 06:11:05 sybreon
+ * Added CMP instruction
+ *
+ * Revision 1.2 2007/04/03 14:46:26 sybreon
+ * Fixed endian correction issues on data bus.
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+// address@hidden
+module aeMB_aslu (/*AUTOARG*/
+ // Outputs
+ dwb_adr_o, rRESULT,
+ // Inputs
+ dwb_dat_i, rBRA, rDLY, rREGA, rREGB, rSIMM, rMXSRC, rMXTGT, rMXALU,
+ rOPC, rPC, rIMM, rRD, rRA, rMXLDST, nclk, nrst, drun, nrun
+ );
+ parameter DSIZ = 32;
+
+ output [DSIZ-1:0] dwb_adr_o;
+ input [31:0] dwb_dat_i;
+
+ output [31:0] rRESULT;
+ input rBRA, rDLY;
+ input [31:0] rREGA, rREGB;
+ input [31:0] rSIMM;
+ input [1:0] rMXSRC,rMXTGT;
+ input [1:0] rMXALU;
+ input [5:0] rOPC;
+ input [31:0] rPC;
+ input [15:0] rIMM;
+ input [4:0] rRD, rRA;
+ input [1:0] rMXLDST;
+
+ input nclk, nrst, drun, nrun;
+
+ reg [31:0] rRESULT, xRESULT;
+ reg rMSR_C, xMSR_C;
+
+ // Endian correction
+ //wire [31:0] wDWBDAT = dwb_dat_i;
+ wire [31:0] wDWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+
+ // Source and Target Select
+ wire [31:0] wOPA =
+ (rMXSRC == 2'b11) ? wDWBDAT :
+ (rMXSRC == 2'b10) ? rRESULT :
+ (rMXSRC == 2'b01) ? rPC :
+ rREGA;
+ wire [31:0] wOPB =
+ (rMXTGT == 2'b11) ? wDWBDAT :
+ (rMXTGT == 2'b10) ? rRESULT :
+ (rMXTGT == 2'b01) ? rSIMM :
+ rREGB;
+
+ // ARITHMETIC
+ //wire wADDC_ = (rOPC[1] & (rMXLDST == 2'o0)) ? rMSR_C : 1'b0;
+ wire wADDC_ = (rOPC[1]) ? rMSR_C : 1'b0;
+ wire wSUBC_ = (rOPC[1]) ? rMSR_C : 1'b1;
+ wire wADDC, wSUBC, wRES_AC,wCMPC;
+ wire [31:0] wADD,wSUB,wRES_A,wCMP;
+
+ // TODO: verify signed compare
+ wire wCMPU = (wOPA > wOPB);
+ wire wCMPF = (rIMM[1]) ? wCMPU :
+ ((wCMPU & ~(wOPB[31] ^ wOPA[31])) | (wOPB[31] &
~wOPA[31]));
+ assign {wCMPC,wCMP} = {wSUBC,wCMPF,wSUB[30:0]};
+ assign {wADDC,wADD} = (wOPB + wOPA) + wADDC_;
+ assign {wSUBC,wSUB} = (wOPB + ~wOPA) + wSUBC_;
+
+ reg rRES_AC;
+ reg [31:0] rRES_A;
+ always @(/*AUTOSENSE*/rIMM or rOPC or wADD or wADDC or wCMP
+ or wCMPC or wSUB or wSUBC)
+ //{rRES_AC,rRES_A} <= #1 (rOPC[0] & ~rOPC[5]) ? {~wSUBC,wSUB} :
{wADDC,wADD};
+ case ({rOPC[5],rOPC[3],rOPC[0],rIMM[0]})
+ 4'h2, 4'h6, 4'h7: {rRES_AC,rRES_A} <= #1 {~wSUBC,wSUB}; // SUB
+ 4'h3: {rRES_AC,rRES_A} <= #1 {~wCMPC,wCMP}; // CMP
+ default: {rRES_AC,rRES_A} <= #1 {wADDC,wADD};
+ endcase // case ({rOPC[5],rOPC[3],rOPC[0],rIMM[0]})
+
+ // LOGIC
+ wire [31:0] wOR = wOPA | wOPB;
+ wire [31:0] wAND = wOPA & wOPB;
+ wire [31:0] wXOR = wOPA ^ wOPB;
+ wire [31:0] wANDN = wOPA & ~wOPB;
+
+ reg [31:0] rRES_L;
+ always @(/*AUTOSENSE*/rOPC or wAND or wANDN or wOR or wXOR)
+ case (rOPC[1:0])
+ 2'o0: rRES_L <= #1 wOR;
+ 2'o1: rRES_L <= #1 wAND;
+ 2'o2: rRES_L <= #1 wXOR;
+ 2'o3: rRES_L <= #1 wANDN;
+ endcase // case (rOPC[1:0])
+
+ // SHIFT
+ wire wSRAC, wSRCC, wSRLC, wRES_SC;
+ wire [31:0] wSRA,wSRC, wSRL, wSEXT8, wSEXT16, wRES_S;
+ assign {wSRAC,wSRA} = {wOPA[0],wOPA[0],wOPA[31:1]};
+ assign {wSRCC,wSRC} = {wOPA[0],rMSR_C,wOPA[31:1]};
+ assign {wSRLC,wSRL} = {wOPA[0],1'b0,wOPA[31:1]};
+ assign wSEXT8 = {{(24){wOPA[7]}},wOPA[7:0]};
+ assign wSEXT16 = {{(16){wOPA[15]}},wOPA[15:0]};
+
+ reg rRES_SC;
+ reg [31:0] rRES_S;
+
+ always @(/*AUTOSENSE*/rIMM or rMSR_C or wSEXT16 or wSEXT8 or wSRA
+ or wSRAC or wSRC or wSRCC or wSRL or wSRLC)
+ case (rIMM[6:5])
+ 2'o0: {rRES_SC,rRES_S} <= #1 {wSRAC,wSRA};
+ 2'o1: {rRES_SC,rRES_S} <= #1 {wSRCC,wSRC};
+ 2'o2: {rRES_SC,rRES_S} <= #1 {wSRLC,wSRL};
+ 2'o3: {rRES_SC,rRES_S} <= #1 (rIMM[0]) ? {rMSR_C,wSEXT16} :
{rMSR_C,wSEXT8};
+ endcase // case (rIMM[6:5])
+
+ // MOVE
+ reg [31:0] rRES_M;
+ always @(/*AUTOSENSE*/rRA or wOPA or wOPB)
+ rRES_M <= #1 (rRA[3]) ? wOPB : wOPA;
+
+ // DWB I/F
+ //assign dwb_adr_o = rRESULT;
+ assign dwb_adr_o = {rRESULT[DSIZ-1:2],2'b00};
+
+ // RESULT + C
+ always @(/*AUTOSENSE*/drun or rMSR_C or rMXALU or rOPC or rRES_A
+ or rRES_AC or rRES_L or rRES_M or rRES_S or rRES_SC)
+ if (drun) begin
+ case (rMXALU)
+ 2'o0: xRESULT <= #1 rRES_A;
+ 2'o1: xRESULT <= #1 rRES_L;
+ 2'o2: xRESULT <= #1 rRES_S;
+ 2'o3: xRESULT <= #1 rRES_M;
+ endcase // case (rMXALU)
+ case (rMXALU)
+ 2'o0: xMSR_C <= #1 (rOPC[2]) ? rMSR_C : rRES_AC;
+ 2'o2: xMSR_C <= #1 rRES_SC;
+ default: xMSR_C <= #1 rMSR_C;
+ endcase // case (rMXALU)
+ end else begin // if (drun)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMSR_C <= 1'h0;
+ xRESULT <= 32'h0;
+ // End of automatics
+ end // else: !if(drun)
+
+ // PIPELINE REGISTER //////////////////////////////////////////////////
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rMSR_C <= 1'h0;
+ rRESULT <= 32'h0;
+ // End of automatics
+ end else if (nrun) begin
+ rRESULT <= #1 xRESULT;
+ rMSR_C <= #1 xMSR_C;
+ end
+
+endmodule // aeMB_aslu
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_control.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,143 @@
+/*
+ * $Id: aeMB_control.v,v 1.3 2007/04/11 04:30:43 sybreon Exp $
+ *
+ * AE68 System Control Unit
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Controls the state of the processor.
+ *
+ * HISTORY
+ * $Log: aeMB_control.v,v $
+ * Revision 1.3 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.2 2007/04/04 14:08:34 sybreon
+ * Added initial interrupt/exception support.
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+// address@hidden
+module aeMB_control (/*AUTOARG*/
+ // Outputs
+ rFSM, nclk, nrst, nrun, frun, drun,
+ // Inputs
+ sys_rst_i, sys_clk_i, sys_int_i, sys_exc_i, rIWBSTB, iwb_ack_i,
+ rDWBSTB, dwb_ack_i, rBRA, rDLY
+ );
+ // System
+ input sys_rst_i, sys_clk_i;
+ input sys_int_i;
+ input sys_exc_i;
+ //input sys_run_i;
+
+ // Instruction WB
+ input rIWBSTB;
+ input iwb_ack_i;
+
+ // Data WB
+ input rDWBSTB;
+ input dwb_ack_i;
+
+ // Internal
+ input rBRA, rDLY;
+ output [1:0] rFSM;
+ //, rLDST;
+ output nclk, nrst, nrun;
+ output frun, drun;
+
+ // Clock code here
+ assign nclk = sys_clk_i;
+
+ // Debounce reset
+ reg [1:0] rRST;
+ assign nrst = rRST[1];
+ always @(posedge nclk or negedge sys_rst_i)
+ if (!sys_rst_i) begin
+ //rNRST <= 2'h3;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rRST <= 2'h0;
+ // End of automatics
+ end else begin
+ rRST <= {rRST[0],1'b1};
+ end
+
+ // Quiet RUN signal
+ assign nrun = ~((rDWBSTB ^ dwb_ack_i) | ((rIWBSTB ^ iwb_ack_i)));
+
+ // Debounce Interrupt/Exception Signals
+ reg [2:0] rEXC, rINT;
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rEXC <= 3'h0;
+ rINT <= 3'h0;
+ // End of automatics
+ end else if (nrun) begin
+ rEXC <= #1 {rEXC[1:0], sys_exc_i};
+ rINT <= #1 {rINT[1:0], sys_int_i};
+ end
+
+ // Machine States
+ parameter [1:0]
+ FSM_RUN = 2'o0,
+ FSM_SWEXC = 2'o3,
+ FSM_HWEXC = 2'o2,
+ FSM_HWINT = 2'o1;
+
+ reg [1:0] rFSM, rNXT;
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rFSM <= 2'h0;
+ // End of automatics
+ end else if (nrun) begin
+ rFSM <= #1 rNXT;
+ end
+
+ always @(/*AUTOSENSE*/rEXC or rFSM or rINT)
+ case (rFSM)
+ FSM_HWEXC: rNXT <= FSM_RUN;
+ //FSM_SWEXC: rNXT <= FSM_RUN;
+ FSM_HWINT: rNXT <= FSM_RUN;
+ default: begin
+ rNXT <= (rEXC == 3'h3) ? FSM_HWEXC :
+ (rINT == 3'h3) ? FSM_HWINT :
+ FSM_RUN;
+ end
+ endcase // case (rFSM)
+
+ // Pause/Bubble
+ reg [1:0] rRUN;
+ assign {drun,frun} = rRUN;
+
+ always @(posedge nclk or negedge nrst)
+ if (!nrst) begin
+ rRUN <= 2'h3;
+ /*AUTORESET*/
+ end else begin
+ rRUN <= #1 {~(rBRA ^ rDLY), ~rBRA};
+ end
+
+endmodule // aeMB_control
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_core.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,224 @@
+/*
+ * $Id: aeMB_core.v,v 1.3 2007/04/11 04:30:43 sybreon Exp $
+ *
+ * AEMB 32-bit Microblaze Compatible Core
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Microblaze compatible, WISHBONE compliant hardware core. This core is
+ * capable of executing software compile for EDK 2.1 using GCC. It has the
+ * capability of handling interrupts as well as exceptions.
+ *
+ * HISTORY
+ * $Log: aeMB_core.v,v $
+ * Revision 1.3 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.2 2007/04/04 06:13:23 sybreon
+ * Removed unused signals
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+module aeMB_core (/*AUTOARG*/
+ // Outputs
+ iwb_stb_o, iwb_adr_o, dwb_we_o, dwb_stb_o, dwb_dat_o, dwb_adr_o,
+ // Inputs
+ sys_rst_i, sys_int_i, sys_exc_i, sys_clk_i, iwb_dat_i, iwb_ack_i,
+ dwb_dat_i, dwb_ack_i
+ );
+ // Instruction WB address space
+ parameter ISIZ = 32;
+ // Data WB address space
+ parameter DSIZ = 32;
+
+ /*AUTOOUTPUT*/
+ // Beginning of automatic outputs (from unused autoinst outputs)
+ output [DSIZ-1:0] dwb_adr_o; // From aslu of aeMB_aslu.v
+ output [31:0] dwb_dat_o; // From regfile of
aeMB_regfile.v
+ output dwb_stb_o; // From decode of aeMB_decode.v
+ output dwb_we_o; // From decode of aeMB_decode.v
+ output [ISIZ-1:0] iwb_adr_o; // From fetch of aeMB_fetch.v
+ output iwb_stb_o; // From decode of aeMB_decode.v
+ // End of automatics
+ /*AUTOINPUT*/
+ // Beginning of automatic inputs (from unused autoinst inputs)
+ input dwb_ack_i; // To control of aeMB_control.v
+ input [31:0] dwb_dat_i; // To regfile of
aeMB_regfile.v, ...
+ input iwb_ack_i; // To control of aeMB_control.v
+ input [31:0] iwb_dat_i; // To fetch of
aeMB_fetch.v, ...
+ input sys_clk_i; // To control of aeMB_control.v
+ input sys_exc_i; // To control of aeMB_control.v
+ input sys_int_i; // To control of aeMB_control.v
+ input sys_rst_i; // To control of aeMB_control.v
+ // End of automatics
+ /*AUTOWIRE*/
+ // Beginning of automatic wires (for undeclared instantiated-module outputs)
+ wire drun; // From control of
aeMB_control.v
+ wire frun; // From control of
aeMB_control.v
+ wire nclk; // From control of
aeMB_control.v
+ wire nrst; // From control of
aeMB_control.v
+ wire nrun; // From control of
aeMB_control.v
+ wire rBRA; // From decode of
aeMB_decode.v
+ wire rDLY; // From decode of
aeMB_decode.v
+ wire rDWBSTB; // From decode of
aeMB_decode.v
+ wire rDWBWE; // From decode of
aeMB_decode.v
+ wire [1:0] rFSM; // From control of
aeMB_control.v
+ wire [15:0] rIMM; // From decode of aeMB_decode.v
+ wire rIWBSTB; // From decode of
aeMB_decode.v
+ wire rLNK; // From decode of
aeMB_decode.v
+ wire [1:0] rMXALU; // From decode of aeMB_decode.v
+ wire [1:0] rMXLDST; // From decode of aeMB_decode.v
+ wire [1:0] rMXSRC; // From decode of aeMB_decode.v
+ wire [1:0] rMXTGT; // From decode of aeMB_decode.v
+ wire [5:0] rOPC; // From decode of aeMB_decode.v
+ wire [31:0] rPC; // From fetch of aeMB_fetch.v
+ wire [4:0] rRA; // From decode of aeMB_decode.v
+ wire [4:0] rRB; // From decode of aeMB_decode.v
+ wire [4:0] rRD; // From decode of aeMB_decode.v
+ wire [4:0] rRD_; // From decode of aeMB_decode.v
+ wire [31:0] rREGA; // From regfile of
aeMB_regfile.v
+ wire [31:0] rREGB; // From regfile of
aeMB_regfile.v
+ wire [31:0] rRESULT; // From aslu of aeMB_aslu.v
+ wire rRWE; // From decode of
aeMB_decode.v
+ wire [31:0] rSIMM; // From decode of aeMB_decode.v
+ // End of automatics
+
+ aeMB_regfile #(DSIZ)
+ regfile (/*AUTOINST*/
+ // Outputs
+ .dwb_dat_o (dwb_dat_o[31:0]),
+ .rREGA (rREGA[31:0]),
+ .rREGB (rREGB[31:0]),
+ // Inputs
+ .dwb_dat_i (dwb_dat_i[31:0]),
+ .rDWBSTB (rDWBSTB),
+ .rDWBWE (rDWBWE),
+ .rRA (rRA[4:0]),
+ .rRB (rRB[4:0]),
+ .rRD (rRD[4:0]),
+ .rRD_ (rRD_[4:0]),
+ .rRESULT (rRESULT[31:0]),
+ .rFSM (rFSM[1:0]),
+ .rPC (rPC[31:0]),
+ .rLNK (rLNK),
+ .rRWE (rRWE),
+ .nclk (nclk),
+ .nrst (nrst),
+ .drun (drun),
+ .nrun (nrun));
+
+ aeMB_fetch #(ISIZ)
+ fetch (/*AUTOINST*/
+ // Outputs
+ .iwb_adr_o (iwb_adr_o[ISIZ-1:0]),
+ .rPC (rPC[31:0]),
+ // Inputs
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .nclk (nclk),
+ .nrst (nrst),
+ .nrun (nrun),
+ .rFSM (rFSM[1:0]),
+ .rBRA (rBRA),
+ .rRESULT (rRESULT[31:0]));
+
+ aeMB_control
+ control (/*AUTOINST*/
+ // Outputs
+ .rFSM (rFSM[1:0]),
+ .nclk (nclk),
+ .nrst (nrst),
+ .nrun (nrun),
+ .frun (frun),
+ .drun (drun),
+ // Inputs
+ .sys_rst_i (sys_rst_i),
+ .sys_clk_i (sys_clk_i),
+ .sys_int_i (sys_int_i),
+ .sys_exc_i (sys_exc_i),
+ .rIWBSTB (rIWBSTB),
+ .iwb_ack_i (iwb_ack_i),
+ .rDWBSTB (rDWBSTB),
+ .dwb_ack_i (dwb_ack_i),
+ .rBRA (rBRA),
+ .rDLY (rDLY));
+
+ aeMB_aslu #(DSIZ)
+ aslu (/*AUTOINST*/
+ // Outputs
+ .dwb_adr_o (dwb_adr_o[DSIZ-1:0]),
+ .rRESULT (rRESULT[31:0]),
+ // Inputs
+ .dwb_dat_i (dwb_dat_i[31:0]),
+ .rBRA (rBRA),
+ .rDLY (rDLY),
+ .rREGA (rREGA[31:0]),
+ .rREGB (rREGB[31:0]),
+ .rSIMM (rSIMM[31:0]),
+ .rMXSRC (rMXSRC[1:0]),
+ .rMXTGT (rMXTGT[1:0]),
+ .rMXALU (rMXALU[1:0]),
+ .rOPC (rOPC[5:0]),
+ .rPC (rPC[31:0]),
+ .rIMM (rIMM[15:0]),
+ .rRD (rRD[4:0]),
+ .rRA (rRA[4:0]),
+ .rMXLDST (rMXLDST[1:0]),
+ .nclk (nclk),
+ .nrst (nrst),
+ .drun (drun),
+ .nrun (nrun));
+
+ aeMB_decode
+ decode (/*AUTOINST*/
+ // Outputs
+ .rSIMM (rSIMM[31:0]),
+ .rMXALU (rMXALU[1:0]),
+ .rMXSRC (rMXSRC[1:0]),
+ .rMXTGT (rMXTGT[1:0]),
+ .rRA (rRA[4:0]),
+ .rRB (rRB[4:0]),
+ .rRD (rRD[4:0]),
+ .rRD_ (rRD_[4:0]),
+ .rOPC (rOPC[5:0]),
+ .rIMM (rIMM[15:0]),
+ .rDWBSTB (rDWBSTB),
+ .rDWBWE (rDWBWE),
+ .rIWBSTB (rIWBSTB),
+ .rDLY (rDLY),
+ .rLNK (rLNK),
+ .rBRA (rBRA),
+ .rRWE (rRWE),
+ .rMXLDST (rMXLDST[1:0]),
+ .iwb_stb_o (iwb_stb_o),
+ .dwb_stb_o (dwb_stb_o),
+ .dwb_we_o (dwb_we_o),
+ // Inputs
+ .rREGA (rREGA[31:0]),
+ .rRESULT (rRESULT[31:0]),
+ .iwb_dat_i (iwb_dat_i[31:0]),
+ .dwb_dat_i (dwb_dat_i[31:0]),
+ .nclk (nclk),
+ .nrst (nrst),
+ .drun (drun),
+ .frun (frun),
+ .nrun (nrun));
+
+endmodule // aeMB_core
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_decode.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,430 @@
+/*
+ * $Id: aeMB_decode.v,v 1.4 2007/04/11 04:30:43 sybreon Exp $
+ *
+ * AEMB Instruction Decoder
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Instruction decoder
+ *
+ * HISTORY
+ * $Log: aeMB_decode.v,v $
+ * Revision 1.4 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.3 2007/04/04 06:12:27 sybreon
+ * Fixed minor bugs
+ *
+ * Revision 1.2 2007/04/03 14:46:26 sybreon
+ * Fixed endian correction issues on data bus.
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+// address@hidden
+module aeMB_decode (/*AUTOARG*/
+ // Outputs
+ rSIMM, rMXALU, rMXSRC, rMXTGT, rRA, rRB, rRD, rRD_, rOPC, rIMM,
+ rDWBSTB, rDWBWE, rIWBSTB, rDLY, rLNK, rBRA, rRWE, rMXLDST,
+ iwb_stb_o, dwb_stb_o, dwb_we_o,
+ // Inputs
+ rREGA, rRESULT, iwb_dat_i, dwb_dat_i, nclk, nrst, drun, frun, nrun
+ );
+ // Internal I/F
+ output [31:0] rSIMM;
+ output [1:0] rMXALU;
+ output [1:0] rMXSRC, rMXTGT;
+ output [4:0] rRA, rRB, rRD, rRD_;
+ output [5:0] rOPC;
+ output [15:0] rIMM;
+ output rDWBSTB, rDWBWE, rIWBSTB;
+ output rDLY, rLNK, rBRA, rRWE;
+ output [1:0] rMXLDST;
+ input [31:0] rREGA, rRESULT;
+
+ // External I/F
+ input [31:0] iwb_dat_i, dwb_dat_i;
+ output iwb_stb_o;
+ output dwb_stb_o, dwb_we_o;
+
+ // System I/F
+ input nclk, nrst, drun, frun, nrun;
+
+ // Endian Correction
+ //wire [31:0] wWBDAT = dwb_dat_i;
+ //wire [31:0] wIREG = iwb_dat_i;
+ wire [31:0] wWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+ wire [31:0] wIREG =
{iwb_dat_i[7:0],iwb_dat_i[15:8],iwb_dat_i[23:16],iwb_dat_i[31:24]};
+
+ // Decode
+ wire [5:0] wOPC = wIREG[31:26];
+ wire [4:0] wRD = wIREG[25:21];
+ wire [4:0] wRA = wIREG[20:16];
+ wire [4:0] wRB = wIREG[15:11];
+ wire [15:0] wIMM = wIREG[15:0];
+
+ // rOPC, rRD, rRA, rRB, rIMM;
+ reg [5:0] rOPC;
+ reg [4:0] rRD, rRA, rRB, rRD_;
+ reg [15:0] rIMM;
+ reg [5:0] xOPC;
+ reg [4:0] xRD, xRA, xRB, xRD_;
+ reg [15:0] xIMM;
+
+ always @(/*AUTOSENSE*/frun or wIMM or wOPC or wRA or wRB or wRD)
+ if (frun) begin
+ xOPC <= wOPC;
+ xRD <= wRD;
+ xRA <= wRA;
+ xRB <= wRB;
+ xIMM <= wIMM;
+ end else begin
+ xOPC <= 6'o40;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xIMM <= 16'h0;
+ xRA <= 5'h0;
+ xRB <= 5'h0;
+ xRD <= 5'h0;
+ // End of automatics
+ end // else: !if(frun)
+
+ always @(/*AUTOSENSE*/drun or rRD)
+ if (drun) begin
+ xRD_ <= rRD;
+ end else begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xRD_ <= 5'h0;
+ // End of automatics
+ end
+
+ // Groups
+ wire fGH0 = (wOPC[5:3] == 3'o0);
+ wire fGH1 = (wOPC[5:3] == 3'o1);
+ wire fGH2 = (wOPC[5:3] == 3'o2);
+ wire fGH3 = (wOPC[5:3] == 3'o3);
+ wire fGH4 = (wOPC[5:3] == 3'o4);
+ wire fGH5 = (wOPC[5:3] == 3'o5);
+ wire fGH6 = (wOPC[5:3] == 3'o6);
+ wire fGH7 = (wOPC[5:3] == 3'o7);
+ wire fGL0 = (wOPC[2:0] == 3'o0);
+ wire fGL1 = (wOPC[2:0] == 3'o1);
+ wire fGL2 = (wOPC[2:0] == 3'o2);
+ wire fGL3 = (wOPC[2:0] == 3'o3);
+ wire fGL4 = (wOPC[2:0] == 3'o4);
+ wire fGL5 = (wOPC[2:0] == 3'o5);
+ wire fGL6 = (wOPC[2:0] == 3'o6);
+ wire fGL7 = (wOPC[2:0] == 3'o7);
+
+ // Decode Logic
+ wire fADD = ({wOPC[5:4],wOPC[0]} == 3'o0);
+ wire fSUB = ({wOPC[5:4],wOPC[0]} == 3'o1);
+ wire fLOGIC = ({wOPC[5:4],wOPC[2]} == 3'o4);
+ wire fMUL = ({wOPC[5:4]} == 3'o1);
+
+ wire fLD = ({wOPC[5:4],wOPC[2]} == 3'o6);
+ wire fST = ({wOPC[5:4],wOPC[2]} == 3'o7);
+
+ wire fBCC = (wOPC[5:4] == 2'b10) & fGL7;
+ wire fBRU = (wOPC[5:4] == 2'b10) & fGL6;
+ wire fBRA = fBRU & wRA[3];
+
+ wire fSHIFT = fGH4 & fGL4;
+ wire fIMM = fGH5 & fGL4;
+ wire fRET = fGH5 & fGL5;
+ wire fMISC = fGH4 & fGL5;
+
+ // MXALU
+ reg [1:0] rMXALU, xMXALU;
+ always @(/*AUTOSENSE*/fBRA or fLOGIC or fSHIFT or frun)
+ if (frun) begin
+ xMXALU <= //(!fNBR) ? 2'o0 :
+ (fSHIFT) ? 2'o2 :
+ (fLOGIC) ? 2'o1 :
+ (fBRA) ? 2'o3 :
+ 2'o0;
+ end else begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMXALU <= 2'h0;
+ // End of automatics
+ end // else: !if(frun)
+
+ // BCC/BRA/RET
+ reg rMXDLY,rMXLNK,xMXDLY,xMXLNK;
+ reg [1:0] rMXBRA,xMXBRA;
+ always @(/*AUTOSENSE*/fBCC or fBRU or fRET or frun or wRA or wRD)
+ if (frun) begin
+ xMXBRA <= //(!fNBR) ? 2'o0 :
+ (fBCC) ? 2'o3 :
+ (fRET) ? 2'o1 :
+ (fBRU) ? 2'o2 :
+ 2'o0;
+ xMXDLY <= //(!fNBR) ? 1'b0 :
+ (fBCC) ? wRD[4] :
+ (fRET) ? 1'b1 :
+ (fBRU) ? wRA[4] :
+ 1'b0;
+ xMXLNK <= //(!fNBR) ? 1'b0 :
+ (fBRU) ? wRA[2] : 1'b0;
+ end else begin // if (frun)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMXBRA <= 2'h0;
+ xMXDLY <= 1'h0;
+ xMXLNK <= 1'h0;
+ // End of automatics
+ end // else: !if(frun)
+
+ // LD ST
+ reg [1:0] rMXLDST,xMXLDST;
+ always @(/*AUTOSENSE*/fLD or fST or frun)
+ if (frun) begin
+ xMXLDST <= //(!fNBR) ? 2'o0 :
+ (fLD) ? 2'o2 :
+ (fST) ? 2'o3 :
+ 2'o0;
+ end else begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMXLDST <= 2'h0;
+ // End of automatics
+ end // else: !if(frun)
+
+ // SRC/TGT - incorporates forwarding
+ reg [1:0] rMXSRC, rMXTGT, rMXALT, xMXSRC,xMXTGT,xMXALT;
+ wire fRWE = (rRD != 5'd0) & (rMXBRA != 2'o3);
+ //wire fFWDBCC = (rMXBRA != 2'o3);
+
+ always @(/*AUTOSENSE*/fBCC or fBRU or fRWE or frun or rMXLDST
+ or rRD or wOPC or wRA or wRB)
+ if (frun) begin
+ xMXSRC <= //(!fNBR) ? 2'o0 :
+ (fBRU|fBCC) ? 2'o1 : // PC
+ ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
+ ((rRD == wRA) & fRWE) ? 2'o2 : // FWD
+ 2'o0; // RA
+ xMXTGT <= //(!fNBR) ? 2'o0 :
+ (wOPC[3]) ? 2'o1 : // IMM
+ ((rRD == wRB) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
+ ((rRD == wRB) & fRWE) ? 2'o2 : // FWD
+ 2'o0; // RB
+ xMXALT <= //(!fNBR) ? 2'o0 :
+ //(fBRU|fBCC) ? 2'o1 : // PC
+ ((rRD == wRA) & (rMXLDST == 2'o2)) ? 2'o3 : // DWB
+ ((rRD == wRA) & fRWE) ? 2'o2 : // FWD
+ 2'o0; // RA
+ end else begin // if (frun)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xMXALT <= 2'h0;
+ xMXSRC <= 2'h0;
+ xMXTGT <= 2'h0;
+ // End of automatics
+ end // else: !if(frun)
+
+ // IMM processing
+ reg [31:0] rSIMM, xSIMM;
+ reg [15:0] rIMMHI, xIMMHI;
+ reg rFIMM, xFIMM;
+
+ always @(/*AUTOSENSE*/fIMM or frun or rFIMM or rIMMHI or wIMM)
+ if (frun) begin
+ xSIMM <= (rFIMM) ? {rIMMHI,wIMM} : {{(16){wIMM[15]}},wIMM};
+ xFIMM <= fIMM;
+ xIMMHI <= (fIMM) ? wIMM : rIMMHI;
+ end else begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xFIMM <= 1'h0;
+ xIMMHI <= 16'h0;
+ xSIMM <= 32'h0;
+ // End of automatics
+ end // else: !if(frun)
+
+ // CC
+ // COMPARATOR
+ //wire [31:0] wREGA = rREGA;
+ wire [31:0] wREGA =
+ (rMXALT == 2'o3) ? wWBDAT :
+ (rMXALT == 2'o2) ? rRESULT :
+ rREGA;
+
+ wire wBEQ = (wREGA == 32'd0);
+ wire wBNE = ~wBEQ;
+ wire wBLT = wREGA[31];
+ wire wBLE = wBLT | wBEQ;
+ wire wBGE = ~wBLT;
+ wire wBGT = ~wBLE;
+
+ reg rBCC;
+ always @(/*AUTOSENSE*/rRD or wBEQ or wBGE or wBGT or wBLE or wBLT
+ or wBNE)
+ case (rRD[2:0])
+ 3'o0: rBCC <= wBEQ;
+ 3'o1: rBCC <= wBNE;
+ 3'o2: rBCC <= wBLT;
+ 3'o3: rBCC <= wBLE;
+ 3'o4: rBCC <= wBGT;
+ 3'o5: rBCC <= wBGE;
+ default: rBCC <= 1'b0;
+ endcase // case (rRD[2:0])
+
+ // Branch Signal
+ reg rBRA, rDLY, rLNK, xBRA, xDLY, xLNK;
+ always @(/*AUTOSENSE*/drun or rBCC or rMXBRA or rMXDLY or rMXLNK)
+ if (drun) begin
+ case (rMXBRA)
+ 2'o0: xBRA <= 1'b0;
+ 2'o3: xBRA <= rBCC;
+ default: xBRA <= 1'b1;
+ endcase // case (rMXBRA)
+
+ case (rMXBRA)
+ 2'o0: xDLY <= 1'b0;
+ 2'o3: xDLY <= rBCC & rMXDLY;
+ default: xDLY <= rMXDLY;
+ endcase // case (rMXBRA)
+
+ case (rMXBRA)
+ 2'o2: xLNK <= rMXLNK;
+ default: xLNK <= 1'b0;
+ endcase // case (rMXBRA)
+ end else begin // if (drun)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xBRA <= 1'h0;
+ xDLY <= 1'h0;
+ xLNK <= 1'h0;
+ // End of automatics
+ end // else: !if(drun)
+
+ // MXRWE
+ reg rRWE, xRWE;
+ wire wRWE = (rRD != 5'd0);
+ always @(/*AUTOSENSE*/drun or rMXBRA or rMXLDST or wRWE)
+ if (drun) begin
+ case (rMXBRA)
+ default: xRWE <= 1'b0;
+ 2'o2: xRWE <= wRWE ^ rMXLDST[0];
+ 2'o0: xRWE <= wRWE;
+ endcase // case (rMXBRA)
+ end else begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xRWE <= 1'h0;
+ // End of automatics
+ end // else: !if(drun)
+
+ // DWB logic
+ reg rDWBSTB, rDWBWE, xDWBSTB, xDWBWE;
+ assign dwb_stb_o = rDWBSTB;
+ assign dwb_we_o = rDWBWE;
+
+ always @(/*AUTOSENSE*/drun or rMXLDST)
+ if (drun) begin
+ xDWBSTB <= rMXLDST[1];
+ xDWBWE <= rMXLDST[0];
+ end else begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xDWBSTB <= 1'h0;
+ xDWBWE <= 1'h0;
+ // End of automatics
+ end
+
+ // WB other signals
+ assign iwb_stb_o = rIWBSTB;
+ assign rIWBSTB = 1'b1;
+
+ // PIPELINE REGISTERS ///////////////////////////////////////////////
+
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ rOPC <= 6'o40;
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rFIMM <= 1'h0;
+ rIMM <= 16'h0;
+ rIMMHI <= 16'h0;
+ rMXALT <= 2'h0;
+ rMXALU <= 2'h0;
+ rMXBRA <= 2'h0;
+ rMXDLY <= 1'h0;
+ rMXLDST <= 2'h0;
+ rMXLNK <= 1'h0;
+ rMXSRC <= 2'h0;
+ rMXTGT <= 2'h0;
+ rRA <= 5'h0;
+ rRB <= 5'h0;
+ rRD <= 5'h0;
+ rSIMM <= 32'h0;
+ // End of automatics
+ end else if (nrun) begin // if (!nrst)
+ rIMM <= #1 xIMM;
+ rOPC <= #1 xOPC;
+ rRA <= #1 xRA;
+ rRB <= #1 xRB;
+ rRD <= #1 xRD;
+
+ rMXALU <= #1 xMXALU;
+ rMXBRA <= #1 xMXBRA;
+ rMXDLY <= #1 xMXDLY;
+ rMXLNK <= #1 xMXLNK;
+ rMXLDST <= #1 xMXLDST;
+
+ rMXSRC <= #1 xMXSRC;
+ rMXTGT <= #1 xMXTGT;
+ rMXALT <= #1 xMXALT;
+
+ rSIMM <= #1 xSIMM;
+ rFIMM <= #1 xFIMM;
+ rIMMHI <= #1 xIMMHI;
+ end // else: !if(!nrst)
+
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rBRA <= 1'h0;
+ rDLY <= 1'h0;
+ rDWBSTB <= 1'h0;
+ rDWBWE <= 1'h0;
+ rLNK <= 1'h0;
+ rRD_ <= 5'h0;
+ rRWE <= 1'h0;
+ // End of automatics
+ end else if (nrun) begin // if (!nrst)
+ rRD_ <= #1 xRD_;
+ rBRA <= #1 xBRA;
+ rDLY <= #1 xDLY;
+ rLNK <= #1 xLNK;
+ rRWE <= #1 xRWE;
+ rDWBSTB <= #1 xDWBSTB;
+ rDWBWE <= #1 xDWBWE;
+ end // else: !if(!nrst)
+
+endmodule // aeMB_decode
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-library-files:("")
+// End:
\ No newline at end of file
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_fetch.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,96 @@
+/*
+ * $Id: aeMB_fetch.v,v 1.3 2007/04/11 04:30:43 sybreon Exp $
+ *
+ * AEMB Instruction Fetch
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Controls the instruction side of AEMB.
+ *
+ * HISTORY
+ * $Log: aeMB_fetch.v,v $
+ * Revision 1.3 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.2 2007/04/04 14:08:34 sybreon
+ * Added initial interrupt/exception support.
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+// address@hidden
+
+module aeMB_fetch (/*AUTOARG*/
+ // Outputs
+ iwb_adr_o, rPC,
+ // Inputs
+ iwb_dat_i, nclk, nrst, nrun, rFSM, rBRA, rRESULT
+ );
+ parameter ISIZ = 32;
+
+ // Instruction WB I/F
+ output [ISIZ-1:0] iwb_adr_o;
+ input [31:0] iwb_dat_i;
+
+ // System
+ input nclk, nrst, nrun;
+
+ // Internal
+ output [31:0] rPC;
+ //output [31:0] rPCNXT;
+ input [1:0] rFSM;
+ input rBRA;
+ input [31:0] rRESULT;
+
+ // WB ADR signal
+ reg [31:0] rIWBADR, rPC, xIWBADR, xPC;
+
+ wire [31:0] wPCNXT = {(rIWBADR[ISIZ-1:2] + 1'b1),2'b00};
+ assign iwb_adr_o = {rIWBADR[ISIZ-1:2],2'b00}; // Word Aligned
+
+ always @(/*AUTOSENSE*/rBRA or rFSM or rIWBADR or rRESULT or wPCNXT)
+ begin
+ // PC Sources - ALU, Direct, Next
+ case (rFSM)
+ //2'b01: xIWBADR <= 32'h00000010; // HWINT
+ //2'b10: xIWBADR <= 32'h00000020; // HWEXC
+ //2'b11: xIWBADR <= #1 32'h00000008; // SWEXC
+ default: xIWBADR <= (rBRA) ? rRESULT : wPCNXT;
+ endcase // case (rFSM)
+
+ xPC <= {rIWBADR[31:2],2'd0};
+ end // always @ (...
+
+ // PIPELINE REGISTERS //////////////////////////////////////////////////
+
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rIWBADR <= 32'h0;
+ rPC <= 32'h0;
+ // End of automatics
+ end else if (nrun) begin
+ rPC <= #1 xPC;
+ rIWBADR <= #1 xIWBADR;
+ end
+
+endmodule // aeMB_fetch
+
\ No newline at end of file
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_regfile.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,430 @@
+/*
+ * $Id: aeMB_regfile.v,v 1.7 2007/04/11 16:30:06 sybreon Exp $
+ *
+ * AEMB Register File
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Implements the 32 registers as registers. Some registers require
+ * special actions during hardware exception/interrupts. Data forwarding
+ * is also taken care of inside here to simplify decode logic.
+ *
+ * HISTORY
+ * $Log: aeMB_regfile.v,v $
+ * Revision 1.7 2007/04/11 16:30:06 sybreon
+ * Cosmetic changes
+ *
+ * Revision 1.6 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.5 2007/04/04 14:08:34 sybreon
+ * Added initial interrupt/exception support.
+ *
+ * Revision 1.4 2007/04/04 06:11:47 sybreon
+ * Fixed memory read-write data hazard
+ *
+ * Revision 1.3 2007/04/03 14:46:26 sybreon
+ * Fixed endian correction issues on data bus.
+ *
+ * Revision 1.2 2007/03/26 12:21:31 sybreon
+ * Fixed a minor bug where RD is trashed by a STORE instruction. Spotted by
Joon Lee.
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+// address@hidden - REG
+// address@hidden - RAM
+module aeMB_regfile(/*AUTOARG*/
+ // Outputs
+ dwb_dat_o, rREGA, rREGB,
+ // Inputs
+ dwb_dat_i, rDWBSTB, rDWBWE, rRA, rRB, rRD, rRD_, rRESULT, rFSM,
+ rPC, rLNK, rRWE, nclk, nrst, drun, nrun
+ );
+ // Data WB bus width
+ parameter DSIZ = 32;
+
+ // Data WB I/F
+ output [31:0] dwb_dat_o;
+ input [31:0] dwb_dat_i;
+
+ // Internal I/F
+ output [31:0] rREGA, rREGB;
+ input rDWBSTB, rDWBWE;
+ input [4:0] rRA, rRB, rRD, rRD_;
+ input [31:0] rRESULT;
+ input [1:0] rFSM;
+ input [31:0] rPC;
+ //, rPCNXT;
+ input rLNK, rRWE;
+ input nclk, nrst, drun, nrun;
+
+ // Register File
+ reg [31:0] r00,r01,r02,r03,r04,r05,r06,r07;
+ reg [31:0] r08,r09,r0A,r0B,r0C,r0D,r0E,r0F;
+ reg [31:0] r10,r11,r12,r13,r14,r15,r16,r17;
+ reg [31:0] r18,r19,r1A,r1B,r1C,r1D,r1E,r1F;
+
+ // FLAGS
+ wire fWE = rRWE & ~rDWBWE;
+ wire fLNK = rLNK;
+ wire fLD = rDWBSTB ^ rDWBWE;
+
+ // PC Latch
+ reg [31:0] rPC_;
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rPC_ <= 32'h0;
+ // End of automatics
+ end else if (nrun) begin
+ rPC_ <= #1 rPC;
+ end
+
+ // DWB data - Endian Correction
+ reg [31:0] rDWBDAT, xDWBDAT;
+ //assign dwb_dat_o = rDWBDAT;
+ //wire [31:0] wDWBDAT = dwb_dat_i;
+ assign dwb_dat_o =
{rDWBDAT[7:0],rDWBDAT[15:8],rDWBDAT[23:16],rDWBDAT[31:24]};
+ wire [31:0] wDWBDAT =
{dwb_dat_i[7:0],dwb_dat_i[15:8],dwb_dat_i[23:16],dwb_dat_i[31:24]};
+
+ // Forwarding Control
+ wire fDFWD = (rRD == rRD_) & fWE;
+ wire fMFWD = rDWBSTB & ~rDWBWE;
+ wire [31:0] wRESULT = (fMFWD) ? wDWBDAT : rRESULT;
+
+ // Register Load
+ always @(/*AUTOSENSE*/drun or fDFWD or r00 or r01 or r02 or r03
+ or r04 or r05 or r06 or r07 or r08 or r09 or r0A or r0B
+ or r0C or r0D or r0E or r0F or r10 or r11 or r12 or r13
+ or r14 or r15 or r16 or r17 or r18 or r19 or r1A or r1B
+ or r1C or r1D or r1E or r1F or rRD or wRESULT)
+ if (drun) begin
+ case (rRD)
+ 5'h00: xDWBDAT <= (fDFWD) ? wRESULT : r00;
+ 5'h01: xDWBDAT <= (fDFWD) ? wRESULT : r01;
+ 5'h02: xDWBDAT <= (fDFWD) ? wRESULT : r02;
+ 5'h03: xDWBDAT <= (fDFWD) ? wRESULT : r03;
+ 5'h04: xDWBDAT <= (fDFWD) ? wRESULT : r04;
+ 5'h05: xDWBDAT <= (fDFWD) ? wRESULT : r05;
+ 5'h06: xDWBDAT <= (fDFWD) ? wRESULT : r06;
+ 5'h07: xDWBDAT <= (fDFWD) ? wRESULT : r07;
+ 5'h08: xDWBDAT <= (fDFWD) ? wRESULT : r08;
+ 5'h09: xDWBDAT <= (fDFWD) ? wRESULT : r09;
+ 5'h0A: xDWBDAT <= (fDFWD) ? wRESULT : r0A;
+ 5'h0B: xDWBDAT <= (fDFWD) ? wRESULT : r0B;
+ 5'h0C: xDWBDAT <= (fDFWD) ? wRESULT : r0C;
+ 5'h0D: xDWBDAT <= (fDFWD) ? wRESULT : r0D;
+ 5'h0E: xDWBDAT <= (fDFWD) ? wRESULT : r0E;
+ 5'h0F: xDWBDAT <= (fDFWD) ? wRESULT : r0F;
+ 5'h10: xDWBDAT <= (fDFWD) ? wRESULT : r10;
+ 5'h11: xDWBDAT <= (fDFWD) ? wRESULT : r11;
+ 5'h12: xDWBDAT <= (fDFWD) ? wRESULT : r12;
+ 5'h13: xDWBDAT <= (fDFWD) ? wRESULT : r13;
+ 5'h14: xDWBDAT <= (fDFWD) ? wRESULT : r14;
+ 5'h15: xDWBDAT <= (fDFWD) ? wRESULT : r15;
+ 5'h16: xDWBDAT <= (fDFWD) ? wRESULT : r16;
+ 5'h17: xDWBDAT <= (fDFWD) ? wRESULT : r17;
+ 5'h18: xDWBDAT <= (fDFWD) ? wRESULT : r18;
+ 5'h19: xDWBDAT <= (fDFWD) ? wRESULT : r19;
+ 5'h1A: xDWBDAT <= (fDFWD) ? wRESULT : r1A;
+ 5'h1B: xDWBDAT <= (fDFWD) ? wRESULT : r1B;
+ 5'h1C: xDWBDAT <= (fDFWD) ? wRESULT : r1C;
+ 5'h1D: xDWBDAT <= (fDFWD) ? wRESULT : r1D;
+ 5'h1E: xDWBDAT <= (fDFWD) ? wRESULT : r1E;
+ 5'h1F: xDWBDAT <= (fDFWD) ? wRESULT : r1F;
+ endcase // case (rRD)
+ end else begin // if (drun)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xDWBDAT <= 32'h0;
+ // End of automatics
+ end // else: !if(drun)
+
+ // Load Registers
+ reg [31:0] xREGA, xREGB;
+ always @(/*AUTOSENSE*/drun or r00 or r01 or r02 or r03 or r04
+ or r05 or r06 or r07 or r08 or r09 or r0A or r0B or r0C
+ or r0D or r0E or r0F or r10 or r11 or r12 or r13 or r14
+ or r15 or r16 or r17 or r18 or r19 or r1A or r1B or r1C
+ or r1D or r1E or r1F or rRA or rRB)
+ if (drun) begin
+ case (rRA)
+ 5'h1F: xREGA <= r1F;
+ 5'h1E: xREGA <= r1E;
+ 5'h1D: xREGA <= r1D;
+ 5'h1C: xREGA <= r1C;
+ 5'h1B: xREGA <= r1B;
+ 5'h1A: xREGA <= r1A;
+ 5'h19: xREGA <= r19;
+ 5'h18: xREGA <= r18;
+ 5'h17: xREGA <= r17;
+ 5'h16: xREGA <= r16;
+ 5'h15: xREGA <= r15;
+ 5'h14: xREGA <= r14;
+ 5'h13: xREGA <= r13;
+ 5'h12: xREGA <= r12;
+ 5'h11: xREGA <= r11;
+ 5'h10: xREGA <= r10;
+ 5'h0F: xREGA <= r0F;
+ 5'h0E: xREGA <= r0E;
+ 5'h0D: xREGA <= r0D;
+ 5'h0C: xREGA <= r0C;
+ 5'h0B: xREGA <= r0B;
+ 5'h0A: xREGA <= r0A;
+ 5'h09: xREGA <= r09;
+ 5'h08: xREGA <= r08;
+ 5'h07: xREGA <= r07;
+ 5'h06: xREGA <= r06;
+ 5'h05: xREGA <= r05;
+ 5'h04: xREGA <= r04;
+ 5'h03: xREGA <= r03;
+ 5'h02: xREGA <= r02;
+ 5'h01: xREGA <= r01;
+ 5'h00: xREGA <= r00;
+ endcase // case (rRA)
+
+ case (rRB)
+ 5'h1F: xREGB <= r1F;
+ 5'h1E: xREGB <= r1E;
+ 5'h1D: xREGB <= r1D;
+ 5'h1C: xREGB <= r1C;
+ 5'h1B: xREGB <= r1B;
+ 5'h1A: xREGB <= r1A;
+ 5'h19: xREGB <= r19;
+ 5'h18: xREGB <= r18;
+ 5'h17: xREGB <= r17;
+ 5'h16: xREGB <= r16;
+ 5'h15: xREGB <= r15;
+ 5'h14: xREGB <= r14;
+ 5'h13: xREGB <= r13;
+ 5'h12: xREGB <= r12;
+ 5'h11: xREGB <= r11;
+ 5'h10: xREGB <= r10;
+ 5'h0F: xREGB <= r0F;
+ 5'h0E: xREGB <= r0E;
+ 5'h0D: xREGB <= r0D;
+ 5'h0C: xREGB <= r0C;
+ 5'h0B: xREGB <= r0B;
+ 5'h0A: xREGB <= r0A;
+ 5'h09: xREGB <= r09;
+ 5'h08: xREGB <= r08;
+ 5'h07: xREGB <= r07;
+ 5'h06: xREGB <= r06;
+ 5'h05: xREGB <= r05;
+ 5'h04: xREGB <= r04;
+ 5'h03: xREGB <= r03;
+ 5'h02: xREGB <= r02;
+ 5'h01: xREGB <= r01;
+ 5'h00: xREGB <= r00;
+ endcase // case (rRB)
+ end else begin // if (drun)
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ xREGA <= 32'h0;
+ xREGB <= 32'h0;
+ // End of automatics
+ end // else: !if(drun)
+
+
+ // Normal Registers
+ wire fR00 = (rRD_ == 5'h00);
+ wire fR01 = (rRD_ == 5'h01);
+ wire fR02 = (rRD_ == 5'h02);
+ wire fR03 = (rRD_ == 5'h03);
+ wire fR04 = (rRD_ == 5'h04);
+ wire fR05 = (rRD_ == 5'h05);
+ wire fR06 = (rRD_ == 5'h06);
+ wire fR07 = (rRD_ == 5'h07);
+ wire fR08 = (rRD_ == 5'h08);
+ wire fR09 = (rRD_ == 5'h09);
+ wire fR0A = (rRD_ == 5'h0A);
+ wire fR0B = (rRD_ == 5'h0B);
+ wire fR0C = (rRD_ == 5'h0C);
+ wire fR0D = (rRD_ == 5'h0D);
+ wire fR0E = (rRD_ == 5'h0E);
+ wire fR0F = (rRD_ == 5'h0F);
+ wire fR10 = (rRD_ == 5'h10);
+ wire fR11 = (rRD_ == 5'h11);
+ wire fR12 = (rRD_ == 5'h12);
+ wire fR13 = (rRD_ == 5'h13);
+ wire fR14 = (rRD_ == 5'h14);
+ wire fR15 = (rRD_ == 5'h15);
+ wire fR16 = (rRD_ == 5'h16);
+ wire fR17 = (rRD_ == 5'h17);
+ wire fR18 = (rRD_ == 5'h18);
+ wire fR19 = (rRD_ == 5'h19);
+ wire fR1A = (rRD_ == 5'h1A);
+ wire fR1B = (rRD_ == 5'h1B);
+ wire fR1C = (rRD_ == 5'h1C);
+ wire fR1D = (rRD_ == 5'h1D);
+ wire fR1E = (rRD_ == 5'h1E);
+ wire fR1F = (rRD_ == 5'h1F);
+
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ r01 <= 32'h0;
+ r02 <= 32'h0;
+ r03 <= 32'h0;
+ r04 <= 32'h0;
+ r05 <= 32'h0;
+ r06 <= 32'h0;
+ r07 <= 32'h0;
+ r08 <= 32'h0;
+ r09 <= 32'h0;
+ r0A <= 32'h0;
+ r0B <= 32'h0;
+ r0C <= 32'h0;
+ r0D <= 32'h0;
+ r0F <= 32'h0;
+ r10 <= 32'h0;
+ r12 <= 32'h0;
+ r13 <= 32'h0;
+ r14 <= 32'h0;
+ r15 <= 32'h0;
+ r16 <= 32'h0;
+ r17 <= 32'h0;
+ r18 <= 32'h0;
+ r19 <= 32'h0;
+ r1A <= 32'h0;
+ r1B <= 32'h0;
+ r1C <= 32'h0;
+ r1D <= 32'h0;
+ r1E <= 32'h0;
+ r1F <= 32'h0;
+ // End of automatics
+ end else begin // if (!nrst)
+ r01 <= #1 (!fR01) ? r01 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r01;
+ r02 <= #1 (!fR02) ? r02 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r02;
+ r03 <= #1 (!fR03) ? r03 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r03;
+ r04 <= #1 (!fR04) ? r04 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r04;
+ r05 <= #1 (!fR05) ? r05 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r05;
+ r06 <= #1 (!fR06) ? r06 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r06;
+ r07 <= #1 (!fR07) ? r07 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r07;
+ r08 <= #1 (!fR08) ? r08 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r08;
+ r09 <= #1 (!fR09) ? r09 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r09;
+ r0A <= #1 (!fR0A) ? r0A : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0A;
+ r0B <= #1 (!fR0B) ? r0B : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0B;
+ r0C <= #1 (!fR0C) ? r0C : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0C;
+ r0D <= #1 (!fR0D) ? r0D : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0D;
+ r0F <= #1 (!fR0F) ? r0F : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0F;
+ r10 <= #1 (!fR10) ? r10 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r10;
+ r12 <= #1 (!fR12) ? r12 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r12;
+ r13 <= #1 (!fR13) ? r13 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r13;
+ r14 <= #1 (!fR14) ? r14 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r14;
+ r15 <= #1 (!fR15) ? r15 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r15;
+ r16 <= #1 (!fR16) ? r16 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r16;
+ r17 <= #1 (!fR17) ? r17 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r17;
+ r18 <= #1 (!fR18) ? r18 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r18;
+ r19 <= #1 (!fR19) ? r19 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r19;
+ r1A <= #1 (!fR1A) ? r1A : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1A;
+ r1B <= #1 (!fR1B) ? r1B : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1B;
+ r1C <= #1 (!fR1C) ? r1C : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1C;
+ r1D <= #1 (!fR1D) ? r1D : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1D;
+ r1E <= #1 (!fR1E) ? r1E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1E;
+ r1F <= #1 (!fR1F) ? r1F : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r1F;
+
+ end // else: !if(!nrst)
+
+ // Special Registers
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ r00 <= 32'h0;
+ r0E <= 32'h0;
+ r11 <= 32'h0;
+ // End of automatics
+ end else begin
+ // R00 - Zero
+ r00 <= #1 r00;
+ // R0E - Interrupt
+ r0E <= #1 //(rFSM == 2'b01) ? rPCNXT :
+ (!fR0E) ? r0E : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r0E;
+ // R11 - Exception
+ r11 <= #1 //(rFSM == 2'b10) ? rPCNXT :
+ (!fR11) ? r11 : (fLD) ? wDWBDAT : (fLNK) ? rPC_ : (fWE) ?
rRESULT : r11;
+ end // else: !if(!nrst)
+
+ // Alternative Design
+ reg [31:0] rMEMA[0:31], rMEMB[0:31], rMEMD[0:31];
+ wire [31:0] wDDAT, wREGA, wREGB, wREGD, wWBDAT;
+ wire wDWE = (fLD | fLNK | fWE) & |rRD_ & nrun;
+ assign wDDAT = (fLD) ? wDWBDAT :
+ (fLNK) ? rPC_ : rRESULT;
+ assign wWBDAT = (fDFWD) ? wRESULT : wREGD;
+
+ assign wREGA = rMEMA[rRA];
+ assign wREGB = rMEMB[rRB];
+ assign wREGD = rMEMD[rRD];
+
+ always @(negedge nclk)
+ if (wDWE) begin
+ rMEMA[rRD_] <= wDDAT;
+ rMEMB[rRD_] <= wDDAT;
+ rMEMD[rRD_] <= wDDAT;
+ end
+
+ // PIPELINE REGISTERS //////////////////////////////////////////////////
+
+ reg [31:0] rREGA, rREGB;
+ always @(/*AUTOSENSE*/wREGA or wREGB)
+ begin
+ //rREGA <= #1 xREGA;
+ //rREGB <= #1 xREGB;
+ rREGA <= #1 wREGA;
+ rREGB <= #1 wREGB;
+ end
+
+ always @(negedge nclk or negedge nrst)
+ if (!nrst) begin
+ /*AUTORESET*/
+ // Beginning of autoreset for uninitialized flops
+ rDWBDAT <= 32'h0;
+ // End of automatics
+ end else if (nrun) begin
+ //rDWBDAT <= #1 xDWBDAT;
+ rDWBDAT <= #1 wWBDAT;
+ end
+
+ // SIMULATION ONLY ///////////////////////////////////////////////////
+ integer i;
+ initial begin
+ for (i=0;i<31;i=i+1) begin
+ rMEMA[i] <= 0;
+ rMEMB[i] <= 0;
+ rMEMD[i] <= 0;
+ end
+ end
+
+ always @(negedge nclk) begin
+ if ((fWE & (rRD_== 5'd0)) || (fLNK & (rRD_== 5'd0)) || (fLD & (rRD_==
5'd0))) $displayh("!!! Warning: Write to R0 !!!");
+ end
+
+endmodule // aeMB_regfile
+
+
+// Local Variables:
+// verilog-library-directories:(".")
+// verilog-library-files:("")
+// End:
\ No newline at end of file
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_testbench.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_testbench.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/aemb/rtl/verilog/aeMB_testbench.v
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,135 @@
+/*
+ * $Id: aeMB_testbench.v,v 1.4 2007/04/11 04:30:43 sybreon Exp $
+ *
+ * AEMB Generic Testbench
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Top level test bench and fake RAM/ROM.
+ *
+ * HISTORY
+ * $Log: aeMB_testbench.v,v $
+ * Revision 1.4 2007/04/11 04:30:43 sybreon
+ * Added pipeline stalling from incomplete bus cycles.
+ * Separated sync and async portions of code.
+ *
+ * Revision 1.3 2007/04/04 14:08:34 sybreon
+ * Added initial interrupt/exception support.
+ *
+ * Revision 1.2 2007/04/04 06:11:59 sybreon
+ * Extended testbench code
+ *
+ * Revision 1.1 2007/03/09 17:52:17 sybreon
+ * initial import
+ *
+ */
+
+module testbench ();
+ parameter ISIZ = 16;
+ parameter DSIZ = 16;
+
+ reg sys_clk_i, sys_rst_i, sys_int_i, sys_exc_i;
+
+ initial begin
+ $dumpfile("aeMB_core.vcd");
+ $dumpvars(1,dut);
+ end
+
+ initial begin
+ sys_clk_i = 1;
+ sys_rst_i = 0;
+ sys_int_i = 0;
+ sys_exc_i = 0;
+ #10 sys_rst_i = 1;
+ #10000 sys_int_i = 1;
+ #100 sys_int_i = 0;
+ end
+
+ initial fork
+ //#100000 $displayh("\nTest Completed.");
+ //#11000 $finish;
+ join
+
+ always #5 sys_clk_i = ~sys_clk_i;
+
+ // FAKE ROM
+ reg [31:0] rom [0:65535];
+ reg [31:0] iwb_dat_i;
+ reg iwb_ack_i, dwb_ack_i;
+ wire [ISIZ-1:0] iwb_adr_o;
+ wire iwb_stb_o;
+ wire dwb_stb_o;
+
+ always @(posedge sys_clk_i) begin
+ iwb_ack_i <= #1 iwb_stb_o;
+ //& $random;
+ dwb_ack_i <= #1 dwb_stb_o;
+ //& $random;
+ iwb_dat_i <= #1 rom[iwb_adr_o[ISIZ-1:2]];
+ end
+
+ // FAKE RAM
+ reg [31:0] ram [0:65535];
+ reg [31:0] dwb_dat_i;
+ reg [31:0] dwblat;
+ wire dwb_we_o;
+ wire [31:0] dwb_dat_o;
+ wire [DSIZ-1:0] dwb_adr_o;
+
+ always @(posedge sys_clk_i) begin
+ ram[dwb_adr_o[DSIZ-1:2]] <= (dwb_we_o & dwb_stb_o) ? dwb_dat_o :
ram[dwb_adr_o[DSIZ-1:2]];
+ dwblat <= dwb_adr_o;
+ dwb_dat_i <= ram[dwb_adr_o[DSIZ-1:2]];
+ end
+
+ integer i;
+ initial begin
+ for (i=0;i<65535;i=i+1) begin
+ ram[i] <= 32'h0;
+ rom[i] <= 32'h0;
+ end
+
+ #1 $readmemh("aeMB.rom",rom);
+ #1 $readmemh("aeMB.rom",ram);
+
+ end
+
+ always @(negedge sys_clk_i) begin
+ if (dwb_stb_o & dwb_we_o & dwb_ack_i)
+ $displayh($stime,"; ST: 0x",dwb_adr_o,"=0x",dwb_dat_o);
+ if (dwb_stb_o & ~dwb_we_o & dwb_ack_i)
+ $displayh($stime,"; LD: 0x",dwb_adr_o,"=0x",dwb_dat_i);
+
+ if ((dwb_adr_o == 16'h8888) && (dwb_dat_o == 32'h7a55ed00))
+ $display("*** SERVICE ***");
+
+ if (dut.control.rFSM == 2'o1)
+ $display("*** INTERRUPT ***");
+
+ end // always @ (posedge sys_clk_i)
+
+ aeMB_core #(ISIZ,DSIZ)
+ dut (
+ .sys_int_i(sys_int_i),.sys_exc_i(sys_exc_i),
+ .dwb_ack_i(dwb_ack_i),.dwb_stb_o(dwb_stb_o),.dwb_adr_o(dwb_adr_o),
+ .dwb_dat_o(dwb_dat_o),.dwb_dat_i(dwb_dat_i),.dwb_we_o(dwb_we_o),
+ .iwb_adr_o(iwb_adr_o),.iwb_dat_i(iwb_dat_i),.iwb_stb_o(iwb_stb_o),
+ .iwb_ack_i(iwb_ack_i),
+ .sys_clk_i(sys_clk_i), .sys_rst_i(sys_rst_i)
+ );
+
+endmodule // testbench
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,3 @@
+/cversim/1.1/Fri Mar 9 17:41:55 2007//
+/iversim/1.1/Fri Mar 9 17:41:55 2007//
+D
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Repository
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Repository
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Repository
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+aemb/sim
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Root
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Root
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Root
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+:pserver:address@hidden:/cvsroot/anonymous
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/CVS/Template
===================================================================
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,7 @@
+#!/bin/sh
+# $Id: cversim,v 1.1 2007/03/09 17:41:55 sybreon Exp $
+# $Log: cversim,v $
+# Revision 1.1 2007/03/09 17:41:55 sybreon
+# initial import
+#
+cver $@ ../rtl/verilog/*.v
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/cversim
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,7 @@
+#!/bin/sh
+# $Id: iversim,v 1.1 2007/03/09 17:41:55 sybreon Exp $
+# $Log: iversim,v $
+# Revision 1.1 2007/03/09 17:41:55 sybreon
+# initial import
+#
+iverilog $@ ../rtl/verilog/*.v && vvp a.out && rm a.out
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sim/iversim
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,2 @@
+/gccrom/1.2/Wed Apr 4 06:14:39 2007//
+D/c////
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Repository
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Repository
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Repository
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+aemb/sw
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Root
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Root
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Root
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+:pserver:address@hidden:/cvsroot/anonymous
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/CVS/Template
===================================================================
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,2 @@
+/aeMB_testbench.c/1.3/Wed Apr 4 14:09:04 2007//
+D
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Repository
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Repository
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Repository
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+aemb/sw/c
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Root
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Root
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Root
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1 @@
+:pserver:address@hidden:/cvsroot/anonymous
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/CVS/Template
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/c/aeMB_testbench.c
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,135 @@
+/*
+ * $Id: aeMB_testbench.c,v 1.3 2007/04/04 14:09:04 sybreon Exp $
+ *
+ * AEMB Function Verification C Testbench
+ * Copyright (C) 2006 Shawn Tan Ser Ngiap <address@hidden>
+ *
+ * This library is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation; either version 2.1 of the License,
+ * or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
+ * License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library; if not, write to the Free Software Foundation,
Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ * DESCRIPTION
+ * Runs a simple test programme that calculates fibonnaci numbers using two
+ * different methods. It tests a whole gamut of operations and is tightly
+ * linked to the ae68_testbench.v testbench module for verification.
+ *
+ * The fibonnaci code is from
+ * http://en.literateprograms.org/Fibonacci_numbers_(C)
+ *
+ * HISTORY
+ * $Log: aeMB_testbench.c,v $
+ * Revision 1.3 2007/04/04 14:09:04 sybreon
+ * Added initial interrupt/exception support.
+ *
+ * Revision 1.2 2007/04/04 06:07:45 sybreon
+ * Fixed C code bug which passes the test
+ *
+ * Revision 1.1 2007/03/09 17:41:57 sybreon
+ * initial import
+ *
+ */
+
+/* Special Prototypes */
+void int_call_func (); // __attribute__((save_volatiles));
+void int_handler_func () __attribute__ ((interrupt_handler));
+
+/* Interrupt Handler */
+void int_handler_func () {
+ int_call_func();
+}
+
+void int_call_func () {
+ int *p;
+ p = 0x88888888;
+ *p = 0x00ED557A; // Write a value to a IO port.
+}
+
+/* Recursive Version */
+
+unsigned int slowfib(unsigned int n)
+{
+ return n < 2 ? n : slowfib(n-1) + slowfib(n-2);
+}
+
+/* Iterative Version */
+
+unsigned int fastfib(unsigned int n)
+{
+ unsigned int a[3];
+ unsigned int *p=a;
+ unsigned int i;
+
+ for(i=0; i<=n; ++i) {
+ if(i<2) *p=i;
+ else {
+ if(p==a) *p=*(a+1)+*(a+2);
+ else if(p==a+1) *p=*a+*(a+2);
+ else *p=*a+*(a+1);
+ }
+ if(++p>a+2) p=a;
+ }
+
+ return p==a?*(p+2):*(p-1);
+}
+
+/* Compare the Results */
+
+int main() {
+ unsigned int n;
+ unsigned int fib_fast, fib_slow;
+ unsigned int fib_lut[] = {0,
+ 1,
+ 1,
+ 2,
+ 3,
+ 5,
+ 8,
+ 13,
+ 21,
+ 34,
+ 55,
+ 89,
+ 144,
+ 233,
+ 377,
+ 610,
+ 987,
+ 1597,
+ 2584,
+ 4181,
+ 6765,
+ 10946,
+ 17711,
+ 28657,
+ 46368,
+ 75025,
+ 121393,
+ 196418,
+ 317811,
+ 514229,
+ 832040,
+ 1346269,
+ 2178309,
+ 3524578,
+ 5702887};
+
+ for (n=0;n<35;n++) {
+ fib_slow = slowfib(n);
+ fib_fast = fastfib(n);
+ while ((fib_fast != fib_lut[n]) || (fib_slow != fib_fast)) {
+ fib_lut[n] = 0x00ED17FA;
+ }
+ }
+
+ return fib_fast;
+}
Added: gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
2007-04-11 20:59:34 UTC (rev 4952)
@@ -0,0 +1,17 @@
+#!/bin/sh
+# $Id: gccrom,v 1.2 2007/04/04 06:14:39 sybreon Exp $
+# $Log: gccrom,v $
+# Revision 1.2 2007/04/04 06:14:39 sybreon
+# Minor changes
+#
+# Revision 1.1 2007/03/09 17:41:56 sybreon
+# initial import
+#
+#mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -mno-clearbss
-msmall-divides -mno-memcpy -mno-xl-gp-opt -o rom.o $@ && \
+mb-gcc -g -mxl-soft-div -mxl-soft-mul -msoft-float -o rom.o $@ && \
+mb-objcopy -O binary rom.o rom.bin && \
+hexdump -v -e'1/4 "%.8X\n"' rom.bin > ../sim/aeMB.rom && \
+mb-objdump -DSC rom.o > rom.dump && \
+rm rom.bin && \
+#mb-run -tv rom.o 2> rom.run && \
+echo "ROM generated"
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/aemb/sw/gccrom
___________________________________________________________________
Name: svn:executable
+ *
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1,2 +1,6 @@
/start.tcl/1.3/Sun May 28 05:00:17 2006//
-D
+D/bench////
+D/doc////
+D/rtl////
+D/sim////
+D/syn////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/bench/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -7,4 +7,8 @@
/eth_miim.v/1.3/Thu Jan 19 14:07:53 2006//
/header.v/1.1/Thu Jan 19 14:07:53 2006//
/reg_int.v/1.4/Fri Nov 17 17:53:07 2006//
-D
+D/MAC_rx////
+D/MAC_tx////
+D/RMON////
+D/TECH////
+D/miim////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/rtl/verilog/TECH/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1,4 +1,5 @@
/CLK_DIV2.v/1.3/Thu Jan 19 14:07:56 2006//
/CLK_SWITCH.v/1.3/Thu Jan 19 14:07:56 2006//
/duram.v/1.2/Thu Jan 19 14:07:56 2006//
-D
+D/altera////
+D/xilinx////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/rtl_sim////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/ncsim_sim////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,6 @@
-D
+D/bin////
+D/data////
+D/log////
+D/out////
+D/run////
+D/script////
Modified: gnuradio/branches/developers/matt/u2f/opencores/i2c/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/i2c/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/i2c/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,8 @@
-D
+D/bench////
+D/doc////
+D/documentation////
+D/rtl////
+D/sim////
+D/software////
+D/verilog////
+D/vhdl////
Modified: gnuradio/branches/developers/matt/u2f/opencores/i2c/bench/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/i2c/bench/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/i2c/bench/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
Modified: gnuradio/branches/developers/matt/u2f/opencores/i2c/doc/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/i2c/doc/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/i2c/doc/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1,2 +1,2 @@
/i2c_specs.pdf/1.3/Thu Jul 3 15:20:47 2003/-kb/
-D
+D/src////
Modified: gnuradio/branches/developers/matt/u2f/opencores/i2c/rtl/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/i2c/rtl/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/i2c/rtl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,2 @@
-D
+D/verilog////
+D/vhdl////
Modified: gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/i2c_verilog////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/run////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/i2c/sim/i2c_verilog/run/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -2,4 +2,5 @@
/ncverilog.key/1.1/Sat Jun 15 07:37:11 2002//
/ncverilog.log/1.1/Sat Jun 15 07:37:11 2002//
/run/1.2/Fri Apr 6 09:02:38 2007//
-D
+D/INCA_libs////
+D/waves////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/i2c/software/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/i2c/software/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/i2c/software/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,2 @@
-D
+D/drivers////
+D/include////
Modified: gnuradio/branches/developers/matt/u2f/opencores/spi/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,4 @@
-D
+D/bench////
+D/doc////
+D/rtl////
+D/sim////
Modified: gnuradio/branches/developers/matt/u2f/opencores/spi/bench/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi/bench/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi/bench/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
Modified: gnuradio/branches/developers/matt/u2f/opencores/spi/doc/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi/doc/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi/doc/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1,2 +1,2 @@
/spi.pdf/1.5/Mon Mar 15 17:46:05 2004/-kb/
-D
+D/src////
Modified: gnuradio/branches/developers/matt/u2f/opencores/spi/rtl/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi/rtl/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi/rtl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
Modified: gnuradio/branches/developers/matt/u2f/opencores/spi/sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi/sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi/sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,2 @@
-D
+D/rtl_sim////
+D/run////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi/sim/rtl_sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi/sim/rtl_sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi/sim/rtl_sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/run////
Modified: gnuradio/branches/developers/matt/u2f/opencores/spi_boot/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi_boot/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi_boot/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -2,4 +2,8 @@
/COPYING/1.1/Tue Feb 8 20:14:49 2005//
/KNOWN_BUGS/1.1/Sun Feb 13 18:28:35 2005//
/README/1.12/Thu Apr 14 21:32:58 2005//
-D
+D/bench////
+D/doc////
+D/rtl////
+D/sim////
+D/sw////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/bench/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi_boot/bench/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi_boot/bench/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/vhdl////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/doc/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi_boot/doc/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi_boot/doc/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1,3 +1,3 @@
/spi_boot.pdf/1.6/Thu Mar 16 17:09:56 2006/-kb/
/spi_boot_schematic.pdf/1.3/Thu Apr 14 21:20:35 2005/-kb/
-D
+D/src////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/vhdl////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/vhdl/CVS/Entries
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/vhdl/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/rtl/vhdl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -12,4 +12,4 @@
/spi_boot_pack-p.vhd/1.1/Tue Feb 8 20:41:33 2005//
/spi_counter-c.vhd/1.1/Tue Feb 8 20:41:33 2005//
/spi_counter.vhd/1.2/Sun Feb 25 18:24:12 2007//
-D
+D/sample////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sim/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sim/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sim/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/rtl_sim////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sw/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sw/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/spi_boot/sw/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/misc////
Modified: gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1,2 @@
-D
+D/bench////
+D/rtl////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/bench/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/bench/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/bench/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
Modified:
gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/CVS/Entries
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/CVS/Entries
2007-04-11 20:49:42 UTC (rev 4951)
+++ gnuradio/branches/developers/matt/u2f/opencores/wb_conbus/rtl/CVS/Entries
2007-04-11 20:59:34 UTC (rev 4952)
@@ -1 +1 @@
-D
+D/verilog////
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- [Commit-gnuradio] r4952 - in gnuradio/branches/developers/matt/u2f/opencores: . aemb aemb/CVS aemb/rtl aemb/rtl/CVS aemb/rtl/verilog aemb/rtl/verilog/CVS aemb/sim aemb/sim/CVS aemb/sw aemb/sw/CVS aemb/sw/c aemb/sw/c/CVS ethernet_tri_mode/CVS ethernet_tri_mode/bench/CVS ethernet_tri_mode/rtl/CVS ethernet_tri_mode/rtl/verilog/CVS ethernet_tri_mode/rtl/verilog/TECH/CVS ethernet_tri_mode/sim/CVS ethernet_tri_mode/sim/rtl_sim/CVS ethernet_tri_mode/sim/rtl_sim/ncsim_sim/CVS i2c/CVS i2c/bench/CVS i2c/doc/CVS i2c/rtl/CVS i2c/sim/CVS i2c/sim/i2c_verilog/CVS i2c/sim/i2c_verilog/run/CVS i2c/software/CVS spi/CVS spi/bench/CVS spi/doc/CVS spi/rtl/CVS spi/sim/CVS spi/sim/rtl_sim/CVS spi_boot/CVS spi_boot/bench/CVS spi_boot/doc/CVS spi_boot/rtl/CVS spi_boot/rtl/vhdl/CVS spi_boot/sim/CVS spi_boot/sw/CVS wb_conbus/CVS wb_conbus/bench/CVS wb_conbus/rtl/CVS,
matt <=