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[Commit-gnuradio] r4953 - in gnuradio/branches/developers/matt/u2f/top:
From: |
matt |
Subject: |
[Commit-gnuradio] r4953 - in gnuradio/branches/developers/matt/u2f/top: safe_bringup u2_basic |
Date: |
Wed, 11 Apr 2007 15:01:30 -0600 (MDT) |
Author: matt
Date: 2007-04-11 15:01:29 -0600 (Wed, 11 Apr 2007)
New Revision: 4953
Added:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Removed:
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Modified:
gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.ise
gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
Log:
just work in u2_basic for now
Modified:
gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
2007-04-11 20:59:34 UTC (rev 4952)
+++ gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v
2007-04-11 21:01:29 UTC (rev 4953)
@@ -12,7 +12,6 @@
module safe_bringup
(
-
// Misc, debug
output led1,
output led2,
@@ -101,9 +100,12 @@
// I2C
input SCL,
input SDA,
- input SCL_force,
- input SDA_force,
+ output SCL_force,
+ output SDA_force,
+ //IOBUF IOPIN11(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_padoen_o));
+ //IOBUF IOPIN2(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_padoen_o));
+
// Clock Gen Control
output [1:0] clk_en,
output [1:0] clk_sel,
@@ -205,6 +207,22 @@
.sclk(sclk),.sdi(sdo),.sdo(sdi) // FIXME these need to be shared
);
-
+ system_control (.aux_clk(),.clk_fpga(),.POR(),
+ .dsp_clk(),.reset_out(),
+ .wb_clk_o(),.wb_rst_o());
+
+
+ i2c_master_top i2c (.wb_clk_i(),.wb_rst_i(),.arst_i(),
+ .wb_adr_i(),.wb_dat_i(),.wb_dat_o(),
+ .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),
+ .wb_ack_o(),.wb_inta_o,
+ .scl_pad_i(),.scl_pad_o(),.scl_padoen_o(),
+ .sda_pad_i(),.sda_pad_o(),.sda_padoen_o() );
+
+ spi_top shared_spi
+ (.wb_clk_i(),.wb_rst_i(),.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),.wb_sel_i(),
+ .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),.wb_ack_o(),.wb_err_o(),.wb_int_o(),
+ .ss_pad_o(),.sclk_pad_o(),.mosi_pad_o(),.miso_pad_i() );
+
endmodule // u2_basic
Deleted: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Copied: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v (from rev
4952, gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.v)
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-11 21:01:29 UTC (rev 4953)
@@ -0,0 +1,228 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name: safe_bringup
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module safe_bringup
+ (
+ // Misc, debug
+ output led1,
+ output led2,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ input [7:0] GMII_TXD,
+ input GMII_TX_EN,
+ input GMII_TX_ER,
+ input GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ input MDIO,
+ input MDC,
+ input PHY_INTn, // open drain
+ input PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ input [17:0] RAM_D,
+ input [18:0] RAM_A,
+ input RAM_CE1n,
+ input RAM_CENn,
+ input RAM_CLK,
+ input RAM_WEn,
+ input RAM_OEn,
+ input RAM_LDn,
+
+ // SERDES
+ input ser_enable,
+ input ser_prbsen,
+ input ser_loopen,
+
+ input ser_tx_clk,
+ input [15:0] ser_t,
+ input ser_tklsb,
+ input ser_tkmsb,
+
+ input ser_rx_clk,
+ input ser_rx_en,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ input spi_cpld_en,
+ input spi_cpld_dout,
+ input spi_cpld_din,
+ input spi_cpld_clk, // temporary bootstrap clock
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ input adc_oen_a,
+ input adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ input adc_oen_b,
+ input adc_pdn_b,
+
+ // DAC
+ input [15:0] dac_a,
+ input [15:0] dac_b,
+
+
+ // I2C
+ input SCL,
+ input SDA,
+ output SCL_force,
+ output SDA_force,
+
+ //IOBUF IOPIN11(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_padoen_o));
+ //IOBUF IOPIN2(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_padoen_o));
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p,
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ input sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ input sen_tx_db,
+ input sclk_tx_db,
+ input sdo_tx_db,
+ input sdi_tx_db,
+
+ input sen_tx_adc,
+ input sclk_tx_adc,
+ input sdo_tx_adc,
+ input sdi_tx_adc,
+
+ input sen_tx_dac,
+ input sclk_tx_dac,
+ input sdi_tx_dac,
+
+ input [15:0] io_tx,
+
+ // RX DBoard
+ input sen_rx_db,
+ input sclk_rx_db,
+ input sdo_rx_db,
+ input sdi_rx_db,
+
+ input sen_rx_adc,
+ input sclk_rx_adc,
+ input sdo_rx_adc,
+ input sdi_rx_adc,
+
+ input sen_rx_dac,
+ input sclk_rx_dac,
+ input sdi_rx_dac,
+
+ input [15:0] io_rx
+ );
+
+ wire clk_fpga;
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFGDS exp_pps_in_pin
(.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+ // defparam exp_pps_out_pin.DRIVE = 12; // FIXME These seem to give
errors...
+ // defparam exp_pps_out_pin.SLEW = "SLOW";
+
+ wire reset;
+ reg [31:0] rst_ctr;
+
+ wire aux_clk = spi_cpld_clk;
+ assign reset = rst_ctr[29];
+
+ always @(posedge aux_clk)
+ rst_ctr <= rst_ctr + 32'd1;
+
+
+ reg [23:0] counter;
+ always @(posedge aux_clk)
+ counter <= #1 counter + 24'd1;
+
+ assign debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
+ assign led1 = counter[23];
+ assign led2 = 1'b0;
+ assign debug_clk[0] = aux_clk;
+ assign debug_clk[1] = clk_fpga;
+
+ clock_control clock_control
+ (.reset(reset),
+ .aux_clk(aux_clk), // 25MHz, for before fpga clock is active
+ .clk_fpga(clk_fpga), // real 100 MHz FPGA clock
+ .clk_en(clk_en), // controls source of reference clock
+ .clk_sel(clk_sel), // controls source of reference clock
+ .clk_func(clk_func), // SYNC or reset to 9510
+ .clk_status(clk_status), // Monitor PLL or SYNC status
+
+ .sen(sen_clk), // Enable for the AD9510
+ .sclk(sclk),.sdi(sdo),.sdo(sdi) // FIXME these need to be shared
+ );
+
+ system_control (.aux_clk(),.clk_fpga(),.POR(),
+ .dsp_clk(),.reset_out(),
+ .wb_clk_o(),.wb_rst_o());
+
+
+ i2c_master_top i2c (.wb_clk_i(),.wb_rst_i(),.arst_i(),
+ .wb_adr_i(),.wb_dat_i(),.wb_dat_o(),
+ .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),
+ .wb_ack_o(),.wb_inta_o,
+ .scl_pad_i(),.scl_pad_o(),.scl_padoen_o(),
+ .sda_pad_i(),.sda_pad_o(),.sda_padoen_o() );
+
+ spi_top shared_spi
+ (.wb_clk_i(),.wb_rst_i(),.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),.wb_sel_i(),
+ .wb_we_i(),.wb_stb_i(),.wb_cyc_i(),.wb_ack_o(),.wb_err_o(),.wb_int_o(),
+ .ss_pad_o(),.sclk_pad_o(),.mosi_pad_o(),.miso_pad_i() );
+
+endmodule // u2_basic
+
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