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[Commit-gnuradio] r4961 - in gnuradio/branches/developers/matt/u2f: cont
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From: |
matt |
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Subject: |
[Commit-gnuradio] r4961 - in gnuradio/branches/developers/matt/u2f: control_lib top/safe_bringup top/u2_basic |
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Date: |
Wed, 11 Apr 2007 19:03:43 -0600 (MDT) |
Author: matt
Date: 2007-04-11 19:03:43 -0600 (Wed, 11 Apr 2007)
New Revision: 4961
Added:
gnuradio/branches/developers/matt/u2f/control_lib/system_contol.v
gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
Modified:
gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.ise
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ise
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
FPGA-specific primitives now in new top level (u2_fpga_top),
with old top level (u2_basic) instantiated inside it.
Added 2 more modules
Added: gnuradio/branches/developers/matt/u2f/control_lib/system_contol.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/system_contol.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/system_contol.v
2007-04-12 01:03:43 UTC (rev 4961)
@@ -0,0 +1,18 @@
+
+
+module system_control (input aux_clk,
+ input clk_fpga,
+ input POR,
+
+ output dsp_clk,
+ output reset_out,
+ output wb_clk_o,
+ output wb_rst_o);
+
+ assign dsp_clk = clk_fpga;
+ assign reset_out = POR;
+ assign wb_rst_o = POR;
+ assign wb_clk_o = aux_clk;
+
+
+endmodule // system_control
Added: gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_output_pins32.v
2007-04-12 01:03:43 UTC (rev 4961)
@@ -0,0 +1,49 @@
+
+
+// Simple 32-bit Wishbone compatible slave output port
+// with 8-bit granularity, modeled after the one in the spec
+// Allows for readback
+// Assumes a 32-bit wishbone bus
+// Lowest order bits get sel[0]
+//
+
+module wb_output_pins32
+ (wb_rst_i, wb_clk_i, wb_dat_i, wb_dat_o,
+ wb_we_i, wb_sel_i, wb_stb_i, wb_ack_o, wb_cyc_i,
+ port_output);
+
+ input wb_rst_i;
+ input wb_clk_i;
+ input wire [31:0] wb_dat_i;
+ output wire [31:0] wb_dat_o;
+ input wb_we_i;
+ input wire [3:0] wb_sel_i;
+ input wb_stb_i;
+ output wb_ack_o;
+ input wb_cyc_i;
+
+ output wire [31:0] port_output;
+
+ reg [31:0] internal_reg;
+
+ always @(posedge wb_clk)
+ if(wb_rst_i)
+ internal_reg <= #1 32'b0;
+ else
+ begin
+ if(wb_stb_i & wb_we_i & wb_sel_i[0])
+ internal_reg[7:0] <= #1 wb_dat_i[7:0];
+ if(wb_stb_i & wb_we_i & wb_sel_i[1])
+ internal_reg[15:8] <= #1 wb_dat_i[15:8];
+ if(wb_stb_i & wb_we_i & wb_sel_i[2])
+ internal_reg[23:16] <= #1 wb_dat_i[23:16];
+ if(wb_stb_i & wb_we_i & wb_sel_i[3])
+ internal_reg[31:24] <= #1 wb_dat_i[31:24];
+ end // else: !if(wb_rst_i)
+
+ assign wb_dat_o = internal_reg;
+ assign port_output = internal_reg;
+ assign wb_ack_o = wb_stb_i;
+
+endmodule // wb_output_pins32
+
Modified:
gnuradio/branches/developers/matt/u2f/top/safe_bringup/safe_bringup.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.ise
===================================================================
(Binary files differ)
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-12 00:48:22 UTC (rev 4960)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-04-12 01:03:43 UTC (rev 4961)
@@ -10,7 +10,7 @@
// Nearly everything is an input
-module safe_bringup
+module u2_basic
(
// Misc, debug
output led1,
@@ -19,10 +19,8 @@
output [1:0] debug_clk,
// Expansion
- input exp_pps_in_p, // Diff
- input exp_pps_in_n, // Diff
- output exp_pps_out_p, // Diff
- output exp_pps_out_n, // Diff
+ input exp_pps_in,
+ output exp_pps_out,
// GMII
// GMII-CTRL
@@ -84,28 +82,26 @@
// ADC
input [13:0] adc_a,
input adc_ovf_a,
- input adc_oen_a,
- input adc_pdn_a,
+ output adc_oen_a,
+ output adc_pdn_a,
input [13:0] adc_b,
input adc_ovf_b,
- input adc_oen_b,
- input adc_pdn_b,
+ output adc_oen_b,
+ output adc_pdn_b,
// DAC
- input [15:0] dac_a,
- input [15:0] dac_b,
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+ // I2C
+ input scl_pad_i,
+ output scl_pad_o,
+ output scl_pad_oen_o,
+ input sda_pad_i,
+ output sda_pad_o,
+ output sda_pad_oen_o,
- // I2C
- input SCL,
- input SDA,
- output SCL_force,
- output SDA_force,
-
- //IOBUF IOPIN11(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_padoen_o));
- //IOBUF IOPIN2(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_padoen_o));
-
// Clock Gen Control
output [1:0] clk_en,
output [1:0] clk_sel,
@@ -113,8 +109,7 @@
input clk_status,
// Clocks
- input clk_fpga_p,
- input clk_fpga_n, // Diff
+ input clk_fpga,
input clk_to_mac,
input pps_in,
@@ -156,44 +151,17 @@
input sen_rx_dac,
input sclk_rx_dac,
input sdi_rx_dac,
-
+
input [15:0] io_rx
);
-
- wire clk_fpga;
- IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
- defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
-
- wire exp_pps_in;
- IBUFGDS exp_pps_in_pin
(.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
- defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
-
- wire exp_pps_out;
- OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
- defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
- // defparam exp_pps_out_pin.DRIVE = 12; // FIXME These seem to give
errors...
- // defparam exp_pps_out_pin.SLEW = "SLOW";
-
- wire reset;
- reg [31:0] rst_ctr;
-
- wire aux_clk = spi_cpld_clk;
- assign reset = rst_ctr[29];
-
- always @(posedge aux_clk)
- rst_ctr <= rst_ctr + 32'd1;
-
- reg [23:0] counter;
- always @(posedge aux_clk)
- counter <= #1 counter + 24'd1;
-
- assign debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
- assign led1 = counter[23];
- assign led2 = 1'b0;
- assign debug_clk[0] = aux_clk;
- assign debug_clk[1] = clk_fpga;
+ wire dsp_clk, wb_clk, wb_rst, POR;
+ wire aux_clk = spi_cpld_clk;
+ assign debug = {clk_status, reset, sen_clk, sclk, sdi, sdo};
+ assign debug_clk[0] = aux_clk;
+ assign debug_clk[1] = clk_fpga;
+
clock_control clock_control
(.reset(reset),
.aux_clk(aux_clk), // 25MHz, for before fpga clock is active
@@ -206,23 +174,59 @@
.sen(sen_clk), // Enable for the AD9510
.sclk(sclk),.sdi(sdo),.sdo(sdi) // FIXME these need to be shared
);
-
- system_control (.aux_clk(),.clk_fpga(),.POR(),
- .dsp_clk(),.reset_out(),
- .wb_clk_o(),.wb_rst_o());
+
+ // 2 Masters
+ // 0 System controller, to set up AD9510 and clocks
+ // 1 Main Processor (aeMB)
+
+ // 11+ Slaves
+ // 0 Output control lines
+ // 1 General SPI
+ // 2 I2C
+ // 3 GPIOs for TX and RX DB
+ // 4 SPI - MDC for ethernet
+ // 5 SPI - TXDB
+ // 6 SPI - TXDAC
+ // 7 SPI - TXADC
+ // 8 SPI - TXDB
+ // 9 SPI - TXDAC
+ // 10 SPI - TXADC
+ // 11 Interrupt controller?
- i2c_master_top i2c (.wb_clk_i(),.wb_rst_i(),.arst_i(),
+ // Output control lines, organized in 4 8-bit segments -- clock, serdes,
adc, led+misc
+ wb_output_pins32 control_lines
+ (.wb_rst_i(wb_rst),.wb_clk_i(wb_clk),.wb_dat_i(),.wb_dat_o(),
+ .wb_we_i(),.wb_sel_i(),.wb_stb_i(),.wb_ack_o(),.wb_cyc_i(),
+ .port_output({) );
+
+ system_control sysctrl (.aux_clk(aux_clk),.clk_fpga(clk_fpga),.POR(),
+ .dsp_clk(dsp_clk),.reset_out(reset),
+ .wb_clk_o(wb_clk),.wb_rst_o(wb_rst));
+
+ i2c_master_top i2c (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(),
.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),
.wb_we_i(),.wb_stb_i(),.wb_cyc_i(),
- .wb_ack_o(),.wb_inta_o,
+ .wb_ack_o(),.wb_inta_o(),
.scl_pad_i(),.scl_pad_o(),.scl_padoen_o(),
.sda_pad_i(),.sda_pad_o(),.sda_padoen_o() );
-
+
spi_top shared_spi
- (.wb_clk_i(),.wb_rst_i(),.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),.wb_sel_i(),
+
(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(),.wb_dat_i(),.wb_dat_o(),.wb_sel_i(),
.wb_we_i(),.wb_stb_i(),.wb_cyc_i(),.wb_ack_o(),.wb_err_o(),.wb_int_o(),
.ss_pad_o(),.sclk_pad_o(),.mosi_pad_o(),.miso_pad_i() );
+
+`define dw 32
+`define aw 16
+`define sw 4
+ wb_conbus_top wb_conbus_top(/*AUTOINST*/);
+
+
endmodule // u2_basic
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+//
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
Added: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_fpga_top.v
2007-04-12 01:03:43 UTC (rev 4961)
@@ -0,0 +1,287 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name: safe_bringup
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+// Nearly everything is an input
+
+module u2_fpga_top
+ (
+ // Misc, debug
+ output led1,
+ output led2,
+ output [31:0] debug,
+ output [1:0] debug_clk,
+
+ // Expansion
+ input exp_pps_in_p, // Diff
+ input exp_pps_in_n, // Diff
+ output exp_pps_out_p, // Diff
+ output exp_pps_out_n, // Diff
+
+ // GMII
+ // GMII-CTRL
+ input GMII_COL,
+ input GMII_CRS,
+
+ // GMII-TX
+ input [7:0] GMII_TXD,
+ input GMII_TX_EN,
+ input GMII_TX_ER,
+ input GMII_GTX_CLK,
+ input GMII_TX_CLK, // 100mbps clk
+
+ // GMII-RX
+ input [7:0] GMII_RXD,
+ input GMII_RX_CLK,
+ input GMII_RX_DV,
+ input GMII_RX_ER,
+
+ // GMII-Management
+ input MDIO,
+ input MDC,
+ input PHY_INTn, // open drain
+ input PHY_RESETn,
+ input PHY_CLK, // possibly use on-board osc
+
+ // RAM
+ input [17:0] RAM_D,
+ input [18:0] RAM_A,
+ input RAM_CE1n,
+ input RAM_CENn,
+ input RAM_CLK,
+ input RAM_WEn,
+ input RAM_OEn,
+ input RAM_LDn,
+
+ // SERDES
+ input ser_enable,
+ input ser_prbsen,
+ input ser_loopen,
+
+ input ser_tx_clk,
+ input [15:0] ser_t,
+ input ser_tklsb,
+ input ser_tkmsb,
+
+ input ser_rx_clk,
+ input ser_rx_en,
+ input [15:0] ser_r,
+ input ser_rklsb,
+ input ser_rkmsb,
+
+ // CPLD interface
+ input spi_cpld_en,
+ input spi_cpld_dout,
+ input spi_cpld_din,
+ input spi_cpld_clk, // temporary bootstrap clock
+
+ // ADC
+ input [13:0] adc_a,
+ input adc_ovf_a,
+ output adc_oen_a,
+ output adc_pdn_a,
+
+ input [13:0] adc_b,
+ input adc_ovf_b,
+ output adc_oen_b,
+ output adc_pdn_b,
+
+ // DAC
+ output [15:0] dac_a,
+ output [15:0] dac_b,
+
+
+ // I2C
+ inout SCL,
+ inout SDA,
+ output SCL_force,
+ output SDA_force,
+
+ // Clock Gen Control
+ output [1:0] clk_en,
+ output [1:0] clk_sel,
+ input clk_func, // FIXME is an input to control the 9510
+ input clk_status,
+
+ // Clocks
+ input clk_fpga_p,
+ input clk_fpga_n, // Diff
+ input clk_to_mac,
+ input pps_in,
+
+ // Generic SPI
+ output sclk,
+ output sen_clk,
+ input sen_dac,
+ output sdi,
+ input sdo,
+
+ // TX DBoard
+ input sen_tx_db,
+ input sclk_tx_db,
+ input sdo_tx_db,
+ input sdi_tx_db,
+
+ input sen_tx_adc,
+ input sclk_tx_adc,
+ input sdo_tx_adc,
+ input sdi_tx_adc,
+
+ input sen_tx_dac,
+ input sclk_tx_dac,
+ input sdi_tx_dac,
+
+ inout [15:0] io_tx,
+
+ // RX DBoard
+ input sen_rx_db,
+ input sclk_rx_db,
+ input sdo_rx_db,
+ input sdi_rx_db,
+
+ input sen_rx_adc,
+ input sclk_rx_adc,
+ input sdo_rx_adc,
+ input sdi_rx_adc,
+
+ input sen_rx_dac,
+ input sclk_rx_dac,
+ input sdi_rx_dac,
+
+ inout [15:0] io_rx
+ );
+
+ wire clk_fpga;
+ IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+ defparam clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+ wire exp_pps_in;
+ IBUFGDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
+ defparam exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+
+ wire exp_pps_out;
+ OBUFDS exp_pps_out_pin
(.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
+ defparam exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+
+ IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_padoen_o));
+ IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_padoen_o));
+
+ // Don't use external transistors for open drain, the FPGA implements this
+ assign SCL_force = 1'b0;
+ assign SDA_force = 1'b0;
+
+ u2_basic u2_basic(/*AUTOINST*/
+ // Outputs
+ .led1 (led1),
+ .led2 (led2),
+ .debug (debug[31:0]),
+ .debug_clk (debug_clk[1:0]),
+ .exp_pps_out (exp_pps_out),
+ .adc_oen_a (adc_oen_a),
+ .adc_pdn_a (adc_pdn_a),
+ .adc_oen_b (adc_oen_b),
+ .adc_pdn_b (adc_pdn_b),
+ .dac_a (dac_a[15:0]),
+ .dac_b (dac_b[15:0]),
+ .scl_pad_o (scl_pad_o),
+ .scl_pad_oen_o (scl_pad_oen_o),
+ .sda_pad_o (sda_pad_o),
+ .sda_pad_oen_o (sda_pad_oen_o),
+ .clk_en (clk_en[1:0]),
+ .clk_sel (clk_sel[1:0]),
+ .sclk (sclk),
+ .sen_clk (sen_clk),
+ .sdi (sdi),
+ // Inputs
+ .exp_pps_in (exp_pps_in),
+ .GMII_COL (GMII_COL),
+ .GMII_CRS (GMII_CRS),
+ .GMII_TXD (GMII_TXD[7:0]),
+ .GMII_TX_EN (GMII_TX_EN),
+ .GMII_TX_ER (GMII_TX_ER),
+ .GMII_GTX_CLK (GMII_GTX_CLK),
+ .GMII_TX_CLK (GMII_TX_CLK),
+ .GMII_RXD (GMII_RXD[7:0]),
+ .GMII_RX_CLK (GMII_RX_CLK),
+ .GMII_RX_DV (GMII_RX_DV),
+ .GMII_RX_ER (GMII_RX_ER),
+ .MDIO (MDIO),
+ .MDC (MDC),
+ .PHY_INTn (PHY_INTn),
+ .PHY_RESETn (PHY_RESETn),
+ .PHY_CLK (PHY_CLK),
+ .RAM_D (RAM_D[17:0]),
+ .RAM_A (RAM_A[18:0]),
+ .RAM_CE1n (RAM_CE1n),
+ .RAM_CENn (RAM_CENn),
+ .RAM_CLK (RAM_CLK),
+ .RAM_WEn (RAM_WEn),
+ .RAM_OEn (RAM_OEn),
+ .RAM_LDn (RAM_LDn),
+ .ser_enable (ser_enable),
+ .ser_prbsen (ser_prbsen),
+ .ser_loopen (ser_loopen),
+ .ser_tx_clk (ser_tx_clk),
+ .ser_t (ser_t[15:0]),
+ .ser_tklsb (ser_tklsb),
+ .ser_tkmsb (ser_tkmsb),
+ .ser_rx_clk (ser_rx_clk),
+ .ser_rx_en (ser_rx_en),
+ .ser_r (ser_r[15:0]),
+ .ser_rklsb (ser_rklsb),
+ .ser_rkmsb (ser_rkmsb),
+ .spi_cpld_en (spi_cpld_en),
+ .spi_cpld_dout (spi_cpld_dout),
+ .spi_cpld_din (spi_cpld_din),
+ .spi_cpld_clk (spi_cpld_clk),
+ .adc_a (adc_a[13:0]),
+ .adc_ovf_a (adc_ovf_a),
+ .adc_b (adc_b[13:0]),
+ .adc_ovf_b (adc_ovf_b),
+ .scl_pad_i (scl_pad_i),
+ .sda_pad_i (sda_pad_i),
+ .clk_func (clk_func),
+ .clk_status (clk_status),
+ .clk_fpga (clk_fpga),
+ .clk_to_mac (clk_to_mac),
+ .pps_in (pps_in),
+ .sen_dac (sen_dac),
+ .sdo (sdo),
+ .sen_tx_db (sen_tx_db),
+ .sclk_tx_db (sclk_tx_db),
+ .sdo_tx_db (sdo_tx_db),
+ .sdi_tx_db (sdi_tx_db),
+ .sen_tx_adc (sen_tx_adc),
+ .sclk_tx_adc (sclk_tx_adc),
+ .sdo_tx_adc (sdo_tx_adc),
+ .sdi_tx_adc (sdi_tx_adc),
+ .sen_tx_dac (sen_tx_dac),
+ .sclk_tx_dac (sclk_tx_dac),
+ .sdi_tx_dac (sdi_tx_dac),
+ .io_tx (io_tx[15:0]),
+ .sen_rx_db (sen_rx_db),
+ .sclk_rx_db (sclk_rx_db),
+ .sdo_rx_db (sdo_rx_db),
+ .sdi_rx_db (sdi_rx_db),
+ .sen_rx_adc (sen_rx_adc),
+ .sclk_rx_adc (sclk_rx_adc),
+ .sdo_rx_adc (sdo_rx_adc),
+ .sdi_rx_adc (sdi_rx_adc),
+ .sen_rx_dac (sen_rx_dac),
+ .sclk_rx_dac (sclk_rx_dac),
+ .sdi_rx_dac (sdi_rx_dac),
+ .io_rx (io_rx[15:0]));
+
+endmodule // u2_fpga_top
+
+// Local Variables:
+// verilog-library-directories:("." "subdir" "subdir2")
+//
verilog-library-files:("/home/matt/u2f/opencores/wb_conbus/rtl/verilog/wb_conbus_top.v")
+// verilog-library-extensions:(".v" ".h")
+// End:
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- [Commit-gnuradio] r4961 - in gnuradio/branches/developers/matt/u2f: control_lib top/safe_bringup top/u2_basic,
matt <=