[Commit-gnuradio] r4962 - in gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src: fpga/lib fpga/rbf/rev2 fpga/rbf/rev4 fpga/toplevel python

[jcorgan]

Author: jcorgan
Date: 2007-04-11 19:34:22 -0600 (Wed, 11 Apr 2007)
New Revision: 4962

Added:
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
Modified:
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
   
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
   gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
Log:
Work in progress, still debugging running DAC's at full rate.

Added: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
                          (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
  2007-04-12 01:34:22 UTC (rev 4962)
@@ -0,0 +1,55 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module dac_interface(clk_i,rst_i,ena_i,tx_i_i,tx_q_i,tx_data_o,tx_sync_o);
+   input clk_i;
+   input rst_i;
+   input ena_i;
+
+   input [15:0] tx_i_i;
+   input [15:0] tx_q_i;
+
+   output [15:0] tx_data_o;
+   output       tx_sync_o;
+
+   wire clk128;
+   reg clk64_d;
+   reg [15:0] tx_data_o;
+   
+   // Create a 128 MHz clock
+   dacpll pll128(.areset(rst_i),.inclk0(clk_i),.c0(clk128));
+
+   // Register the clk64 clock in the clk128 domain
+   always @(posedge clk128)
+     begin
+       if (rst_i | ~ena_i)
+         clk64_d <= 1'b0;
+       else
+         clk64_d <= clk_i;
+     end
+
+   assign tx_sync_o = clk64_d;
+   
+   // Register the tx data in the clk128 domain
+   always @(posedge clk128)
+         tx_data_o <= clk64_d ? tx_i_i : tx_q_i;
+
+endmodule // dac_interface


Property changes on: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/lib/dac_interface.v
___________________________________________________________________
Name: svn:executable
   + *

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev2/usrp_sar.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/rbf/rev4/usrp_sar.rbf
===================================================================
(Binary files differ)

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
    2007-04-12 01:03:43 UTC (rev 4961)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/dacpll.v
    2007-04-12 01:34:22 UTC (rev 4962)
@@ -91,7 +91,7 @@
                altpll_component.clk0_divide_by = 1,
                altpll_component.clk0_duty_cycle = 50,
                altpll_component.clk0_multiply_by = 2,
-               altpll_component.clk0_phase_shift = "4000",
+               altpll_component.clk0_phase_shift = "3000",
                altpll_component.compensate_clock = "CLK0",
                altpll_component.inclk0_input_frequency = 15625,
                altpll_component.intended_device_family = "Cyclone",
@@ -192,7 +192,7 @@
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
-// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "5.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
@@ -224,7 +224,7 @@
 // Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
-// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "5000"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
        2007-04-12 01:03:43 UTC (rev 4961)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.qsf
        2007-04-12 01:34:22 UTC (rev 4962)
@@ -367,6 +367,8 @@
 
 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition 
-to | -section_id Top
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+
+set_global_assignment -name VERILOG_FILE ../lib/dac_interface.v
 set_global_assignment -name VERILOG_FILE dacpll.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/cordic_stage.v
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/cordic.v
@@ -385,4 +387,4 @@
 set_global_assignment -name VERILOG_FILE ../../../../usrp/fpga/sdr_lib/rssi.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/rx_dcoffset.v
 set_global_assignment -name VERILOG_FILE 
../../../../usrp/fpga/sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE usrp_sar.v
+set_global_assignment -name VERILOG_FILE usrp_sar.v
\ No newline at end of file

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-12 01:03:43 UTC (rev 4961)
+++ 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/fpga/toplevel/usrp_sar.v
  2007-04-12 01:34:22 UTC (rev 4962)
@@ -107,7 +107,7 @@
    // Transmit Side
 
    wire [15:0] tx_i, tx_q;
-   reg  [15:0] tx_a_reg;
+   wire [15:0] tx_data;
    wire [15:0] tx_debug;
 
    // Transmitter creates a new output sample per clk64
@@ -115,19 +115,13 @@
                      
.saddr_i(serial_addr),.sdata_i(serial_data),.s_strobe_i(serial_strobe),
                      .tx_i_o(tx_i),.tx_q_o(tx_q),.debug_o(tx_debug));
 
-   // This "re-creates" the AD9862 CLKOUT2 signal as CLKOUT2 is not wired to 
the FPGA
-   // The PLL phase must be experimentally determined
-   wire clk128;
-   dacpll pll128(.areset(rst_i),.inclk0(clk64),.c0(clk128));
-   always @(posedge clk128)
-     tx_a_reg <= clk64 ? tx_i : tx_q;
-   
-   assign TXSYNC_A = clk64;
-   assign tx_a = tx_a_reg[15:2];
 
+   dac_interface 
dac_interface(.clk_i(clk64),.rst_i(sar_reset),.ena_i(enable_tx),
+                              
.tx_i_i(tx_i),.tx_q_i(tx_q),.tx_data_o(tx_data),.tx_sync_o(TXSYNC_A));
 
+   assign tx_a = tx_data[15:2];
    assign tx_b = 14'b0;
-   assign TXSYNC_B = 0;
+   assign TXSYNC_B = 1'b0;
    
    
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
    // Receive Side

Modified: 
gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py
===================================================================
--- gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py  
2007-04-12 01:03:43 UTC (rev 4961)
+++ gnuradio/branches/developers/jcorgan/sar-fe/gr-sar-fe/src/python/sar_tx.py  
2007-04-12 01:34:22 UTC (rev 4962)
@@ -13,6 +13,7 @@
         self.set_tx_dig(0x11)
        self.set_tx_dll(0x49)
         self.set_tx_clkout(0x00)
+       self.set_amplitude(32000)
         
     def set_amplitude(self, amplitude):
        self.trans._write_fpga_reg(usrp.FR_USER_0, int(amplitude))