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[Commit-gnuradio] r4974 - in gnuradio/branches/developers/thottelt: . in
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From: |
thottelt |
|
Subject: |
[Commit-gnuradio] r4974 - in gnuradio/branches/developers/thottelt: . inband/usrp/fpga/toplevel/usrp_std tx_data |
|
Date: |
Thu, 12 Apr 2007 16:39:24 -0600 (MDT) |
Author: thottelt
Date: 2007-04-12 16:39:24 -0600 (Thu, 12 Apr 2007)
New Revision: 4974
Added:
gnuradio/branches/developers/thottelt/tx_data/
gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers.v
gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers_test.v
gnuradio/branches/developers/thottelt/tx_data/data_packet_fifo.v
gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
Log:
channel block prototype
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
===================================================================
---
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
2007-04-12 21:03:06 UTC (rev 4973)
+++
gnuradio/branches/developers/thottelt/inband/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
2007-04-12 22:39:24 UTC (rev 4974)
@@ -27,7 +27,7 @@
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 3.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "00:14:04 JULY 13,
2003"
-set_global_assignment -name LAST_QUARTUS_VERSION 6.1
+set_global_assignment -name LAST_QUARTUS_VERSION "5.1 SP1"
# Pin & Location Assignments
# ==========================
Added: gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers.v
===================================================================
--- gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers.v
2007-04-12 22:39:24 UTC (rev 4974)
@@ -0,0 +1,145 @@
+module chan_fifo_readers
+ ( input reset,
+ input tx_clock,
+ input [31:0]adc_clock,
+ input [15:0]data_bus,
+ input WR,
+ input debug,
+ input pkt_complete,
+ output reg [15:0]tx_q,
+ output reg [15:0]tx_i,
+ output reg overrun,
+ output reg underrun) ;
+
+ // States
+ `define IDLE 4'd0
+ `define READ 4'd1
+ `define HEADER1 4'd2
+ `define HEADER2 4'd3
+ `define TIMESTAMP1 4'd4
+ `define TIMESTAMP2 4'd5
+ `define WAIT 4'd6
+ `define SENDWAIT 4'd7
+ `define SEND 4'd8
+ `define DISCARD 4'd9
+
+ // fifo inputs
+ reg skip;
+ reg rdreq;
+
+ // fifo ouputs
+ wire [15:0] fifodata;
+ wire pkt_waiting;
+
+ // Channel fifo
+ data_packet_fifo tx_usb_fifo
+ ( .reset(reset),
+ .clock_in(tx_clock),
+ .clock_out(tx_clock),
+ .ram_data_in(data_bus),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .pkt_complete(pkt_complete),
+ .skip_packet(skip)
+ );
+
+ // State registers
+ reg[3:0] reader_state;
+ reg[3:0] reader_next_state;
+
+ //Variables
+ reg[8:0] payload_len;
+ reg[8:0] read_len;
+ reg[31:0] timestamp;
+ reg burst;
+
+ always @(posedge tx_clock)
+ begin
+ if (reset) begin
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ overrun <= 0;
+ underrun <= 0;
+ burst <= 0;
+ end
+ else begin
+ reader_state = reader_next_state;
+ case (reader_state)
+ `IDLE: begin
+ reader_next_state <= (pkt_waiting & debug)? `READ : `IDLE;
+ rdreq <= (pkt_waiting & debug);
+ end
+ `READ: begin
+ reader_next_state <= `HEADER1;
+ end
+ `HEADER1: begin
+ reader_next_state <= `HEADER2;
+ end
+ `HEADER2: begin
+ payload_len <= (fifodata & 16'h1FF);
+ read_len <= 9'd0;
+ reader_next_state <= `TIMESTAMP1;
+ end
+ `TIMESTAMP1: begin
+ timestamp <= {fifodata, 16'b0};
+ rdreq <= 0;
+ reader_next_state <= `TIMESTAMP2;
+ end
+ `TIMESTAMP2: begin
+ timestamp <= timestamp + fifodata;
+ reader_next_state <= `WAIT;
+ end
+ `WAIT: begin
+ if (timestamp > adc_clock + 5) begin
+ reader_next_state <= `WAIT;
+ end
+ else if (timestamp < adc_clock + 5
+ && timestamp > adc_clock) begin
+ reader_next_state <= `SENDWAIT;
+ rdreq <= 1;
+ end
+ else if (timestamp < adc_clock) begin
+ reader_next_state <= `DISCARD;
+ skip <= 1;
+ end
+ end
+
+ `SENDWAIT: begin
+ reader_next_state <= `SEND;
+ end
+
+ `SEND: begin
+ read_len <= read_len + 2;
+
+ // If end of payload...
+ if (read_len == payload_len) begin
+ reader_next_state <= `DISCARD;
+ skip <= (payload_len < 508);
+ end
+ else begin
+ if (read_len == payload_len - 4)
+ rdreq <= 0;
+ // Forward data
+ tx_q <= fifodata;
+ end
+ end
+ `DISCARD: begin
+ skip <= 0;
+ reader_next_state <= `IDLE;
+ end
+
+
+ default: begin
+ $display ("Error unknown state");
+ reader_state <= `IDLE;
+ reader_next_state <= `IDLE;
+ end
+ endcase
+ end
+ end
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers.v
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers_test.v
===================================================================
--- gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers_test.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers_test.v
2007-04-12 22:39:24 UTC (rev 4974)
@@ -0,0 +1,114 @@
+module chan_fifo_readers_test();
+
+// Inputs
+reg reset;
+reg txclock;
+reg [15:0] data_bus;
+reg [31:0] ttime;
+reg WR;
+reg adcclock;
+reg debug;
+reg pkt_complete;
+wire [15:0] tx_q;
+wire [15:0] tx_i;
+wire overrun;
+wire underrun;
+
+chan_fifo_readers chan (
+ .reset(reset),
+ .tx_clock(txclock),
+ .adc_clock(ttime),
+ .data_bus(data_bus),
+ .WR(WR),
+ .debug(debug),
+ .pkt_complete(pkt_complete),
+ .tx_q(tx_q),
+ .tx_i(tx_i),
+ .overrun(overrun),
+ .underrun(underrun));
+
+
+reg [15:0] i ;
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ adcclock = 0;
+ txclock = 0;
+ data_bus = 0;
+ WR = 0;
+ i = 0 ;
+ ttime = 0;
+ debug = 0;
+ pkt_complete = 0;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge txclock)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (20) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+ if (i == 3)
+ data_bus = 1000;
+ else if (i == 1)
+ data_bus = 32;
+ else if (i == 2)
+ data_bus = 0;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ if (i == 19)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+
+ repeat (12) begin
+ @(posedge txclock)
+ pkt_complete <= 0;
+ WR = 1'b1 ;
+ if (i == 3)
+ data_bus = 1600;
+ else if (i == 1)
+ data_bus = 16;
+ else if (i == 2)
+ data_bus = 0;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ if (i == 11)
+ pkt_complete <= 1;
+ end
+
+ WR <= 0;
+ i = 0;
+ pkt_complete <= 0;
+ debug = 1;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
+ end
+
+always@(posedge adcclock) begin
+ ttime <= ttime + 1;
+end
+
+always
+ #5 txclock = ~txclock ;
+
+always
+ #1 adcclock = ~adcclock ;
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/thottelt/tx_data/chan_fifo_readers_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/tx_data/data_packet_fifo.v
===================================================================
--- gnuradio/branches/developers/thottelt/tx_data/data_packet_fifo.v
(rev 0)
+++ gnuradio/branches/developers/thottelt/tx_data/data_packet_fifo.v
2007-04-12 22:39:24 UTC (rev 4974)
@@ -0,0 +1,109 @@
+module data_packet_fifo
+ ( input reset,
+ input clock_in,
+ input clock_out,
+ input [15:0]ram_data_in,
+ input write_enable,
+ output reg [15:0]ram_data_out,
+ output reg pkt_waiting,
+ input read_enable,
+ input pkt_complete,
+ input skip_packet) ;
+
+ /* Some parameters for usage later on */
+ parameter DATA_WIDTH = 16 ;
+ parameter NUM_PACKETS = 4 ;
+
+ /* Create the RAM here */
+ reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
+
+ /* Create the address signals */
+ reg [7:0] usb_ram_offset_out ;
+ reg [1:0] usb_ram_packet_out ;
+ reg [7:0] usb_ram_offset_in ;
+ reg [1:0] usb_ram_packet_in ;
+
+ wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
+ wire [7-2+NUM_PACKETS:0] usb_ram_ain ;
+
+ assign usb_ram_aout = {usb_ram_packet_out, usb_ram_offset_out} ;
+ assign usb_ram_ain = {usb_ram_packet_in, usb_ram_offset_in} ;
+
+ // Check if there is one full packet to process
+ always @(usb_ram_ain, usb_ram_aout)
+ begin
+ if (reset)
+ pkt_waiting <= 0;
+ else if (usb_ram_ain >= usb_ram_aout)
+ pkt_waiting <= usb_ram_ain - usb_ram_aout >= 256;
+ else
+ pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >=
256;
+ end
+
+ /* RAM Write Address process */
+ always @(posedge clock_in)
+ begin
+ if( reset )
+ begin
+ usb_ram_offset_in <= 0 ;
+ usb_ram_packet_in <= 0 ;
+ end
+ else
+ if( pkt_complete )
+ begin
+ usb_ram_packet_in <= usb_ram_packet_in + 1;
+ usb_ram_offset_in <= 0;
+ end
+ else if( write_enable )
+ begin
+ if (usb_ram_offset_in == 8'b11111111)
+ begin
+ usb_ram_offset_in <= 0;
+ usb_ram_packet_in <= usb_ram_packet_in + 1;
+ end
+ else
+ usb_ram_offset_in <= usb_ram_offset_in + 1 ;
+ end
+ end
+
+ /* RAM Writing process */
+ always @(posedge clock_in)
+ begin
+ if( write_enable )
+ begin
+ usb_ram[usb_ram_ain] <= ram_data_in ;
+ end
+ end
+
+ /* RAM Read Address process */
+ always @(posedge clock_out)
+ begin
+ if( reset )
+ begin
+ usb_ram_packet_out <= 0 ;
+ usb_ram_offset_out <= 0 ;
+ end
+ else
+ if( skip_packet )
+ begin
+ usb_ram_packet_out <= usb_ram_packet_out + 1 ;
+ usb_ram_offset_out <= 0 ;
+ end
+ else if(read_enable) begin
+ if( usb_ram_offset_out == 8'b11111111 )
+ begin
+ usb_ram_offset_out <= 0 ;
+ usb_ram_packet_out <= usb_ram_packet_out + 1 ;
+ end
+ else
+ usb_ram_offset_out <= usb_ram_offset_out + 1 ;
+ end
+ end
+
+ /* RAM Reading Process */
+ always @(posedge clock_out)
+ begin
+ ram_data_out <= usb_ram[usb_ram_aout] ;
+ end
+
+endmodule
Property changes on:
gnuradio/branches/developers/thottelt/tx_data/data_packet_fifo.v
___________________________________________________________________
Name: svn:executable
+ *
Added: gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf
(rev 0)
+++ gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf 2007-04-12
22:39:24 UTC (rev 4974)
@@ -0,0 +1,286 @@
+[Library]
+
+; Altera specific primitive library mappings
+
+vital2000 = $MODEL_TECH/../vital2000
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+std = $MODEL_TECH/../std
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+apex20k = $MODEL_TECH/../altera/vhdl/apex20k
+apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
+apexii = $MODEL_TECH/../altera/vhdl/apexii
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
+flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
+flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
+max = $MODEL_TECH/../altera/vhdl/max
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+stratix = $MODEL_TECH/../altera/vhdl/stratix
+stratixii = $MODEL_TECH/../altera/vhdl/stratixii
+cyclone = $MODEL_TECH/../altera/vhdl/cyclone
+cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
+apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
+apexii_ver = $MODEL_TECH/../altera/verilog/apexii
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
+flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
+flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
+max_ver = $MODEL_TECH/../altera/verilog/max
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+stratix_ver = $MODEL_TECH/../altera/verilog/stratix
+stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
+cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
+cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
+stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
+
+work = work
+[vcom]
+; Turn on VHDL-1993 as the default. Normally is off.
+; VHDL93 = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; .ini file has Explict enable so that std_logic_signed/unsigned
+; will match synthesis tools behavior.
+ Explicit = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = false
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off inclusion of debugging info within design units. Default is to
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+
+; RequireConfigForAllDefaultBinding = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units. Default is to
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turns on incremental compilation of modules
+; Incremental = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ns
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 0 ns
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; License = plus
+
+; Stop the simulator after an assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+;CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format. For VHDL, PathSeparator = /
+; for Verilog, PathSeparator = .
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated
+; else open files on first read or write
+; DelayFileOpen = 0
+
+; Control VHDL files opened for write
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control number of VHDL files open concurrently
+; This number should always be less then the
+; current ulimit setting for max file descriptors
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; This controls the number of hierarchical regions displayed as
+; part of a signal name shown in the waveform window. The default
+; value or a value of zero tells VSIM to display the full name.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit
+; packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Don't quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is to be compressed.
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+[Project]
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 4
+Project_File_0 = Z:/wc/tx_data/data_packet_fifo.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176407747 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 1
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_1 = Z:/wc/tx_usb/usb_packet_fifo.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1175460531 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 2
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_2 = Z:/wc/tx_data/chan_fifo_readers_test.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176408575 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 3
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = Z:/wc/tx_data/chan_fifo_readers.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1176407505 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 0
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_Sim_Count = 0
+Project_Folder_Count = 0
+Echo_Compile_Output = 0
+Save_Compile_Report = 1
+Project_Opt_Count = 0
+ForceSoftPaths = 0
+ReOpenSourceFiles = 1
+VERILOG_DoubleClick = Edit
+VERILOG_CustomDoubleClick =
+VHDL_DoubleClick = Edit
+VHDL_CustomDoubleClick =
+PSL_DoubleClick = Edit
+PSL_CustomDoubleClick =
+TEXT_DoubleClick = Edit
+TEXT_CustomDoubleClick =
+SYSTEMC_DoubleClick = Edit
+SYSTEMC_CustomDoubleClick =
+TCL_DoubleClick = Edit
+TCL_CustomDoubleClick =
+MACRO_DoubleClick = Edit
+MACRO_CustomDoubleClick =
+VCD_DoubleClick = Edit
+VCD_CustomDoubleClick =
+SDF_DoubleClick = Edit
+SDF_CustomDoubleClick =
+XML_DoubleClick = Edit
+XML_CustomDoubleClick =
+LOGFILE_DoubleClick = Edit
+LOGFILE_CustomDoubleClick =
+EditorState = {tabbed horizontal 1} {Z:/wc/tx_usb/usb_packet_fifo.v 0 1}
{Z:/wc/tx_usb/usb_fifo_reader.v 0 0} {Z:/wc/tx_data/data_packet_fifo.v 0 0}
{Z:/wc/tx_data/chan_fifo_readers_test.v 0 0}
+Project_Major_Version = 6
+Project_Minor_Version = 1
Property changes on: gnuradio/branches/developers/thottelt/tx_data/tx_data.mpf
___________________________________________________________________
Name: svn:executable
+ *
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