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[Commit-gnuradio] r5031 - gnuradio/branches/developers/matt/u2f/control_
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From: |
matt |
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Subject: |
[Commit-gnuradio] r5031 - gnuradio/branches/developers/matt/u2f/control_lib |
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Date: |
Tue, 17 Apr 2007 02:06:24 -0600 (MDT) |
Author: matt
Date: 2007-04-17 02:06:24 -0600 (Tue, 17 Apr 2007)
New Revision: 5031
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
Log:
fixes for synthesis
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
2007-04-17 03:35:37 UTC (rev 5030)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_bootstrap_rom.v
2007-04-17 08:06:24 UTC (rev 5031)
@@ -2,11 +2,33 @@
module clock_bootstrap_rom(input [15:0] addr, output [47:0] data);
- reg [47:0] rom [0:1023];
+ reg [47:0] rom [0:15];
- initial
- $readmemh("bootrom.mem", rom);
+ //initial
+ // $readmemh("bootrom.mem", rom);
assign data = rom[addr];
+ initial
+ begin
+ // First 16 bits are address, last 32 are data
+ // First 4 bits of address select which slave
+ rom[0] = 48'h0000_0C00_0F03; // Both clk sel choose ext ref (0), both
are enabled (1), turn off SERDES, ADCs, turn on leds
+ rom[1] = 48'h1014_0000_0000; // SPI: Set Divider to div by 2
+ rom[2] = 48'h1018_0000_0001; // SPI: Choose AD9510
+ rom[3] = 48'h1010_0000_3418; // SPI: Auto-slave select, interrupt
when done, TX_NEG, 24-bit word
+ rom[4] = 48'h1000_0000_0010; // SPI: AD9510 A:0 D:10 Set up AD9510
SPI
+ rom[5] = 48'h1010_0000_3518; // SPI: SEND IT Auto-slave select,
interrupt when done, TX_NEG, 24-bit word
+ rom[6] = 48'hffff_ffff_ffff; // terminate
+ rom[7] = 48'hffff_ffff_ffff; // terminate
+ rom[8] = 48'hffff_ffff_ffff; // terminate
+ rom[9] = 48'hffff_ffff_ffff; // terminate
+ rom[10] = 48'hffff_ffff_ffff; // terminate
+ rom[11] = 48'hffff_ffff_ffff; // terminate
+ rom[12] = 48'hffff_ffff_ffff; // terminate
+ rom[13] = 48'hffff_ffff_ffff; // terminate
+ rom[14] = 48'hffff_ffff_ffff; // terminate
+ rom[15] = 48'hffff_ffff_ffff; // terminate
+ end // initial begin
+
endmodule // clock_bootstrap_rom
Modified: gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
2007-04-17 03:35:37 UTC (rev 5030)
+++ gnuradio/branches/developers/matt/u2f/control_lib/clock_control.v
2007-04-17 08:06:24 UTC (rev 5031)
@@ -33,48 +33,48 @@
output [1:0] clk_sel, // controls source of reference clock
input clk_func, // FIXME needs to be some kind of out SYNC or
reset to 9510
input clk_status, // Monitor PLL or SYNC status
-
+
output sen, // Enable for the AD9510
output sclk, // FIXME these need to be shared
input sdi,
output sdo
);
-
+
wire read = 1'b0; // Always write for now
wire [1:0] w = 2'b00; // Always send 1 byte at a time
- assign clk_sel = 2'b00; // Both outputs from External Ref (SMA)
- assign clk_en = 2'b11; // Both outputs enabled
-
- reg [20:0] addr_data;
- // reg [7:0] data;
- reg [5:0] entry;
- reg start;
- reg [7:0] counter;
- reg [23:0] command;
+ assign clk_sel = 2'b00; // Both outputs from External Ref (SMA)
+ assign clk_en = 2'b11; // Both outputs enabled
+ reg [20:0] addr_data;
+
+ reg [5:0] entry;
+ reg start;
+ reg [7:0] counter;
+ reg [23:0] command;
+
always @*
case(entry)
6'd00 : addr_data = {13'h00,8'h10}; // Serial setup
- 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives
distribution, everything on
- 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1,
normal levels
- 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div
by 1)
- 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det,
Charge Pump normal
- 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump
current
- 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation,
Prescalar Div by 2, PLL On
- 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits)
- 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits),
Div by 1
- 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal,
Dig Lock Det
- 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect -
LOR causes failure...
- 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't
Care
- 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0
- 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5
+ 6'd01 : addr_data = {13'h45,8'h00}; // CLK2 drives distribution,
everything on
+ 6'd02 : addr_data = {13'h3D,8'h80}; // Turn on output 1, normal levels
+ 6'd03 : addr_data = {13'h4B,8'h80}; // Bypass divider 1 (div by 1)
+ 6'd04 : addr_data = {13'h08,8'h47}; // POS PFD, Dig LK Det, Charge
Pump normal
+ 6'd05 : addr_data = {13'h09,8'h70}; // Max Charge Pump current
+ 6'd06 : addr_data = {13'h0A,8'h04}; // Normal operation, Prescalar
Div by 2, PLL On
+ 6'd07 : addr_data = {13'h0B,8'h00}; // RDIV MSB (6 bits)
+ 6'd08 : addr_data = {13'h0C,8'h01}; // RDIV LSB (8 bits), Div by 1
+ 6'd09 : addr_data = {13'h0D,8'h00}; // Everything normal, Dig Lock Det
+ 6'd10 : addr_data = {13'h07,8'h00}; // Disable LOR detect - LOR
causes failure...
+ 6'd11 : addr_data = {13'h04,8'h00}; // A Counter = Don't Care
+ 6'd12 : addr_data = {13'h05,8'h00}; // B Counter MSB = 0
+ 6'd13 : addr_data = {13'h06,8'h05}; // B Counter LSB = 5
default : addr_data = {13'h5A,8'h01}; // Register Update
endcase // case(entry)
wire [5:0] lastentry = 6'd15;
- wire done = (counter == 8'd49);
-
+ wire done = (counter == 8'd49);
+
always @(posedge aux_clk)
if(reset)
begin
@@ -106,11 +106,10 @@
if(~counter[0])
command <= {command[22:0],1'b0};
end
-
+
assign sen = (done | counter == 8'd0); // CSB is high when we're not doing
anything
assign sclk = ~counter[0];
assign sdo = command[23];
-
endmodule // clock_control
Modified: gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
2007-04-17 03:35:37 UTC (rev 5030)
+++ gnuradio/branches/developers/matt/u2f/control_lib/system_control.v
2007-04-17 08:06:24 UTC (rev 5031)
@@ -1,5 +1,3 @@
-
-
// This module is a WB master. It sets up the clocks
// and resets based on the power-on reset
@@ -28,7 +26,7 @@
always @(posedge POR or posedge aux_clk)
if(POR)
begin
- wb_rst_o = 1'b1;
+ wb_rst_o <= 1'b1;
finished <= #1 1'b0;
start <= #1 1'b0;
started <= #1 1'b0;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
2007-04-17 03:35:37 UTC (rev 5030)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_bus_writer.v
2007-04-17 08:06:24 UTC (rev 5031)
@@ -8,7 +8,7 @@
module wb_bus_writer (input start,
output done,
- output [15:0] rom_addr,
+ output reg [15:0] rom_addr,
input [47:0] rom_data,
// WB Master Interface, don't need wb_dat_i
input wb_clk_i,
@@ -24,14 +24,11 @@
`define IDLE 0
`define READ 1
-`define SEND 2
-`define WAIT 3
reg [3:0] state;
- reg [15:0] rom_addr;
-
- wire done = (state != `IDLE) && (&rom_data); // Done
when we see all 1s
+ assign done = (state != `IDLE) && (&rom_data); // Done
when we see all 1s
+
always @(posedge wb_clk_i)
if(wb_rst_i)
begin
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